UCC21520: UCC21520: High Side Failure

Hi Pranit,

Thanks for your interest in our driver.

Quickly looking at your schematic:

-You're using an isolated driver but it looks like you may not the isolation given that PGND and SGND are shortly through the single Ferrite bead point.

-Bootstrap cap and VDD cap must be sized appropriately typically for CVDD >= 10Cboot to fully charge the boot cap.

-What is PN of the boot diode used? is it rated for the expected Vbus?

While we're further reviewing your schematic and layout, please refer to the attached document to appropriately size the bootstrap components and the decoupling capacitors. Once we updated those components on the board, let's remove the load first and focus on the driver and IGBT at the same bus voltages previously tested to confirm or rule out the bootstrap components. 

https://www.ti.com/lit/an/slua887/slua887.pdf

We will will review your schematic and layout to get back to you with additional comments and feedback early next week (Tuesday at the latest, Dallas time).

Thanks.

Regards,

-Mamadou

Hi,

Yes, I'm not using the isolation currently, but will it cause an issue?

Secondly, the boot diode is a schottky diode

Vf = 0.14v, Vrr = 40v, If = 4A

I don't understand how does the DC bus affect the diode rating?

Thanks for pointing out the Cbypass value for bootstrap supply. I'll change the C_bypass value to 4.7uF and Cboot to 0.1uF. Is that fine? (because if I keep Cboot to 4.7uF, getting a 47uF smd ceramic capacitor is quite difficult.)

For an IGBT with Ciss = 2.4nF, Cboot = 0.1uF and Cbypass = 4.7uF falls safely in recommended values

Hi Pranit,

The bootstrap diode needs to be able to block Vsw+Vboot. Please see section 9.2.2.2 of the datasheet, where we recommend a diode with a rating higher than the DC link voltage.

When your DC link + Vboot goes higher than the 40-V rating of your diode, it is likely avalanching and causing these issues. I recommend using a diode with a higher Vr rating, at least 120% of your expected maximum switch node voltage. Please remember to include overshoot and ringing into your maximum switch node voltage.

If this helped answer your question, could you please press the green button? If not, feel free to ask more questions.

Thanks and best regards,

John

Hi,

Yes, I understood the bootstrap diode rating. Thank you! I changed the bootstrap diode and the bootstrap supply capacitors. I also changed the Cboot to 100uF and put 100uF cap on bootstrap supply and the LS supply too. However, the problem still persists. Inface

I soldered a new phase and tested with a new driver, still I'm getting the distortion at same DC-Link level (~40v @100ohm+10mH load). I did a test to further narrow down the plausible causes. Under loaded conditions, I pulled a MCU pin HIGH and monitored its state, just to verify whether is it only the PWM pin causing the issue or is it a system level problem. When distortion occurred, the MCU wasn't able to hold that pin constantly HIGH. Instead the same distortions occurred in the HIGH state of the pin. 

Again, this whole distortion phenomenon occurs only when load is connected to the DC bus i.e when HS switch is ON. 

I'd like to ask, is there any problem in the layout? Is there any problem with the selected RC values on the board? I had a look at all the reference designs of UCC21520, and the gate driver designs they have are far simpler than what I have on my board. Only thing remaining to do is to isolate the signal ground and power ground. Apart from that, what other factors can be causing this issue?

This is what my assembled circuit looks like (feel free to point out any issues)

Hi Pranit,

It could definitely be a input signal integrity issue. Can you do a double pulse test and zoom in on each of the rising and falling waveforms? It’s also possible that the low-side FET is being turned on by parasitic Cgd capacitance which might cause switch node oscillation. What are the FET part numbers?

This does look similar to the waveforms in this app note written by my colleague – which shows the importance of layout and filters.

http://www.ti.com/lit/an/slua897/slua897.pdf

You can also use the same layout best practices covered in the app ntoe for this driver. Comparing the schematic capture to the layout, it looks like the reference designators changed, so it's hard to correlate schematic to layout.

I don’t think increasing the bootstrap capacitance will help in this situation. It might actually decrease performance if the capacitor is too big and takes a long time to charge.

If this helped answer your question, could you please press the green button? If not, feel free to ask more questions.

Thanks and best regards,

John

Hi John!

Initially the circuit had only 2 grounds - SGND (MCU+ UCC i/p) and PGND (UCC o/p + IGBTs). Noise coupled from the power loop to the control loop. So, I isolated SGND and PGND, still the input integrity was compromised.

Finally, I isolated the MCU, UCC21520 and power loop. I provided gate pulses to the driver via an optocoupler. So, now I have 3 grounds on my entire system - MCU gnd, Opto gnd and Power Gnd.

MCU Gnd = SGND (only microcontroller here)
Opto Gnd  = Primary Gnd (shared by opto output and UCC's primary side)
Power Gnd = PGND (shared by IGBTs, DC-Link and Bootstrap supply)

The system works fine at 60V DC-Link. But at ~90VDC, I start seeing the HS output getting distorted, despite HS input being stable. I initially suspected two factors - 
1. Input signal distortion
2. Bootstrap failure
However, both of these were fine. It was only the output getting distorted mysteriously at 90+ VDC-Link. I'm attaching the graphs below

### Checking INPUT SIGNAL INTEGRITY ###

### Checking OUTPUT SIGNAL INTEGRITY ###

Distortion1 (~80V DC-Link)

Distortion2 (~100V DC-Link)

Note that the Duty cycle of the HS output changes on its own, even when the HS input duty cycle remains unchanged

I have Cboot = 100uF and VDD-Boot bypass = 100uF (oversized intentionally).This doesn't seem to be a failure due to input distortion. All inputs are good, all supplies are good and used as per TI's recommendation.. Layout is made as per TI recommendations. I even double checked the values and layout with the TIDA 00366 note and TIDA-01540 note. 

The entire debugging process is consuming a lot of time and its getting annoying. Kindly get back to this problem. I'd be glad if you could point out any issues in the layout

Hi Pranit,

What are the values of C6 and R4 on your board? We recommend using >2.2nF capacitor for C6. This helps improve noise immunity of the DT circuit. If noise is getting into the DT circuit, it could cause false triggering of the DT circuit.

Also, your scope captures are being taken at a sample rate of 10MS/s. This limits your scope’s effective bandwidth and will mask higher frequency measurements. In order to truly rule out input signal integrity, you will likely need to take measurements with a sample rate > 350MS/s.

I would try the DT cap and resistor settings first, though.

Thanks,

John

Hi John,

I changed the DT capacitor to 330nF, the issue still persists. At high DC-link, HS output gets corrupted - switching ON/OFF at HF within its ON period. Complete isolation of primary and secondary didn't solve the issue either. In every case, the HS failed. Recently, beyond 140VDC-Link, the HS suddenly stopped giving any pulse despite its input being intact. Unlike HS, LS worked fine every time.

I think I'll switch to a dedicated HS-LS driver with isolated supplies. For reasons unknown, the circuit mentioned in UCC21520's datasheet and related App Notes didn't work for me.

Hi Pranit,

Thanks for the update. Please keep us in mind if you have any additional questions.

Thanks,

John

Hi,

I switched to a galvanically isolated dual driver, slowed down turn-ON/OFF process and limited the bootstrapping current to even lower value. The circuit is working fine now at high DC-Link voltages. 

Two things bothered me - 
1. CMTI limit violation. (corrected it by increasing turnON-OFF time)
2. Burning of BS current limiting resistor (rather unusual and unexpected)
    This can happen only when high current flows through the BS path and this can happen if the Cboot is too high 
So why does the datasheet mention select Cboot > 10*Ciss (why isn't there an upper limit on Cboot?)/
Rboot burned and went into MOhm range causing BS current to be in uA range. So, Cboot didn't charge and that explains constant LOW pulse on HS output.

I'd like to suggest few amendments in the datasheets - 
1. Mention CMTI and its effects, extensively. 
2. Link all resources in one single document (datasheet or some design guideline)
    It'd speed up designing and debugging if resources like ref designs, layout considerations, design guidelines, troubleshooting, possible failures, lectures etc are linked to in one single piece of document.

Nevertheless, I'd conclude that UCC21520 didn't fail, its the supporting circuitry which failed causing the driver to fail. I believe UCC will work too if turn-ON/OFF is slowed down and BS resistors are changed.

Hi John!

About the LS Vgs spike, yes it's happening due to HS turn on, however, it isn't causing a shoot-through. If you look closely at the Vgs spike interval, I-load is still constant and also VDS-LS is rising. The spike in I-load is probably caused due to reverse recovery of body diode. Whatever the reason maybe, I-load spike is not due to shoot-through.

About Rboot, I changed the diode (40v to 1kv) first and then operated the phase. Even after diode replacement, the resistor burned. So I replaced the resistor and now everything is working fine. 

About CMTI, even I feel its a herculean task for the IGBT itself to switch at 100v/ns slew, but since a TI lecture highlighted the exact same phenomenon and attributed it to CMTI, I think CMTI may be the culprit. However, is it possible that at high DC-Link Rboot somehow drew large current causing it to heat up and increase resistance (hence its inability to charge Cboot. Sounds irrelevant, but HS not being able to turn ON hints at BS output failure (Rboot, Cboot). 

Hi Pranit,

How are you measuring I-load? Usually, shoot-through current will bypass the load and drain through the low-side power device.

Did you replace the resistor at the same time as the diode? The resistor could have been damaged at the same time as the 40V diode.

Thanks,

John