TPS92513HV: Max PWM frequency and RT/CLK Pin

Hello Adrian,

It is not recommended to PWM the TPS92513HV at 15-20 KHz though it may work.  Contrast ratio will be significantly reduced.  Rise and Fall time of the inductor current can cause non-linear dimming and regulation issues.  The recommended range is 100 Hz to 1 KHz, it can be used beyond this with limitations on dimming performance that depend on the design such as Input voltage, Output voltage, switching frequency and inductor value.  The t_rise and t_fall are small compared to the current slew rate of the inductor.

The TPS92513HV can work this way.  It takes time for the TPS92513HV to switch from RT switching frequency to external synchronized switching frequency.  It has to meet the criteria below.  Is this a dynamic change or something set once the load conditions are known?  This would be something to try and see how it behaves when implementing this.  I would look at current regulation to make sure it remains stable due to changing ripple current.  Also, as stated below, switching in and out of this mode is not desirable since the converter drops switching frequency to 150 KHz which can cause issues in some designs (designs intended for higher switching frequency).  The sync capacitor and resistor are also needed as stated below and is shown in Figure 12 of the datasheet.

From the datasheet:

8.3.3 Synchronizing the Switching Frequency to an External Clock (RT/CLK Pin)
The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square
wave to the RT/CLK pin through the circuit network as shown in Figure 12. The square wave amplitude must
transition lower than 0.63 V and higher than 1.81 V on the RT/CLK pin and have an on-time greater than 51 ns
and an off-time greater than 100 ns. The synchronization frequency range is 300 kHz to 2 MHz. The rising edge
of the PH is synchronized to the falling edge of RT/CLK pin signal. The internal oscillator provides default
switching frequency set by connecting the resistor from the RT/CLK pin to ground should the synchronization
signal turn off.

It is required to AC couple the synchronization signal through a 470 pF ceramic capacitor and a 4 kΩ series
resistor to the RT/CLK pin. The series resistor reduces PH jitter in heavy load applications when synchronizing to
an external clock and in applications which transition from synchronizing to RT mode. The first time the RT/CLK
pin is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The
internal 0.5 V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock
onto the external signal. Since there is a PLL on the regulator, the switching frequency can be higher or lower
than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode
and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100
microseconds.
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz, then reapplies the 0.5 V voltage and the resistor then sets the switching frequency. It is
not recommended that a system transition from PLL mode to resistor mode repeatedly during operation. When
the PLL loses the external clock input the default 150 kHz switching frequency creates long on-times, which
result in higher inductor ripple currents. This can lead to inductor saturation if the system is not designed to
operate at this frequency.

Best Regards,