UCC21750: Minimum ON TIME

Hi Andrew,

Thanks for your help promoting our drivers. 

Are you looking to determine the minimum on-time of the buck converter? If so, you will need to determine the FETs that the IC will be driving (gate charge, etc... and gate drive voltage, desired dv/dt of the FETs to appropriately determine required peak current out of the driver and set the external gate resistance.

You would also want to keep in mind the propagation delays of the IC in addition to the PWD parameter in the d/s that will essentially impact the minimum PWM pulse width. 

Assuming the buck converter topology, you also want to keep in mind the part-to-part skew of the ICs to adequately account for dead-time and dead-time losses of the converter.

Regards,

-Mamadou

Hi Andrew,

The input (IN+/IN+) deglitch filter, T_INFIL, is typically 40ns. This means the minimum input pulsewidth is 40ns. You can find more details of the definition of this spec in Section 7.2 of the UCC21750 datasheet. You may also consider the potential for pulse width distortion, PWD, which may cause the pulse width to be longer depending on process variation. Additionally, rise and fall times at the output dependent on the load is also going to affect the minimum pulse width. 

Additionally, the maximum frequency specification is 1 MHz.

If this answers your question, please hit the green button!

Regards,

Audrey