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Hello,
Can you please explain further how the new design did not work?
Additionally, can you provide a schematic, or was the transformer the only component changed?
Lastly, there is no R421 on the diagram, can you specify which resistor is in question?
Thank you!
Regards,
Michael Pahl
Hello,
Thank you for providing your schematic. I see now that you attached it the first time and I missed it.
As for R421, it is the biasing resistor for the opto-coupler. This resistor is calculated by:
Where Rob is the resistor we want to calculate. This is taken from the application note fr your reference: http://www.ti.com/lit/an/slva305c/slva305c.pdf
It appears there are equations in the schematic that refer to some of the values in the above equation.
Regards,
Michael Pahl
I don't understand the data of 150mV from what;
Vref =1.24V;
Vled=1.1V;
Iled=2mA;
Rob is calculated to 1.255K;
so I can make the Rob to 1.2K?
Hello,
The equation is trying to calculate the voltage drop across the resistor. The 150mV is from the TLV431 datasheet, to take into account the voltage created by the current through the bottom biasing resistor.
I would factor this into your equation.
Hello,
The 150mV is added into the equation for marginal error. This topic is discussed at length in the following post:
https://e2e.ti.com/support/power-management/f/196/t/323424?TPS23753A-Question-about-SLVA305C
It can be ignored, or changed if you want more margin in the design. Since your design is working I would confirm you could ignore it.
Regards,
Michael Pahl
Thank you for your reply
I think I should learn this part of the circuit well
Now the circuit is ready to work. I tested the load of 2A with no problem;
Now the problem is that my working circuit requires little current. Under normal conditions, 5.5v /1A can meet the operating conditions.The maximum current test will not exceed 2A;At ordinary times, the working current is about 500mA;Therefore, the current efficiency of this circuit is very low, and the working current at ordinary times does not reach 1/4 of the full load.
Maybe I should go back to the circuit plan.Can you give me some advice?POE needs to support ieee 802.3af/at
Hello,
If you look at the efficiency of the TI EVMs with the TPS23754 you will see that the efficiency drops at lower load currents. This is the nature of these designs.
Some things you can do is find FETs with lower Rdson. That is one major area of power loss. Another is the transformer, if you could find a more efficient one. Additionally, the snubber circuits contribute to power loss. In most designs they are necessary for preventing overshoot, but this circuit is one to look at for optimization.
In the future, since this is a different question, I would kindly ask that you create a new post so we can keep threads limited to one question. Thank you!
Regards,
Michael Pahl