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TPS65381A-Q1: Question on TPS65381A behavior - configurable VBATP_OV protection at 36V

Part Number: TPS65381A-Q1

Dear Team,

One of my customers has been evaluating TPS65381A and they have a questions. please see details below:

According to the datasheet TPS65381A is supposed to work at 36V. However NRES is pulled low at about 35.7V while all the voltage outputs are normal.

Is it an expected behaviour? If not how can we fix this?

Note that we are not communicating with TPS65381A, so it remains in its default configuration.

Could you please help on this?

Best Regards,

Caglar

  • Hello Caglar,

     

    The TPS65381A-Q1 operates up to a nominal 36 V on the supply pins (VBATP and VBAT_SAFING, assumed to be tie together on the PCB by a VBAT net of low impedance). There is the VBATP over voltage protection in the device that will set the VBATP_OV flag and by default configuration cause RESET state to protect the device from supplying the normal system level current while the input voltage is near or above 36 V.   Please note the absolute maximum for the supply pins is 40 V.

     

    The VBAT_OV thresholds are specified in the electrical specification of the device in POS 6.4 for rising and POS 6.5 for falling (to clear the VBATP_OV bit and release the RESET state).

     


     

    The device offers configurability if you want this VBATP overvoltage protection bit to automatically transition the device to RESET state via the MASK_VBATP_OV bit in DEV_CFG2 register. By default this bit is cleared to 0 so the protection feature is enabled and will cause a transition of the device to RESET state once the VBATP_OVrise threshold has been reached (34.7 V to 36.7 V).

     

    If you want the device to operate until the abs maximum voltage, the software should set the MASK_VBATP_OV bit in DEV_CFG2 register to 1 so the device will not transition to RESET state once the VBATP_OVrise threshold has been reached.

     

    Further documented on this bit and the state machine reaction may be found in the description for the RESET state (section 5.4.21 of the datasheet), device controller state diagram (section 5.4.19 of the datasheet) and the descrition in DEV_CFG2 Register description (section 5.5.3.3.2) of the datasheet.