Dear TI,
I'm about to implement interrupt for digital comparator in ADC. After reading the documentation I know that the digital comparator can use the upper and lower limit for checking the converted value and assert the interrupt flag. However it is still not clear to me if the interrupt is level-driven and signalled anew as long as the converted value stays out of the limit, or is it signalled only once when the comparator detects the converted value crossing the limit (then no new interrupt until the converted value comes back into the limit and goes out again). Could you, please, explain this to me?
Best regards,
Adam
