WEBENCH® Tools/LM3409HV: LM3409HV & 6A Load

Hello Asif,

could you attach the schematic or sent it to me via email.  I will send an email so you know where to send it.  I will also need to know the input voltage range, output voltage and range.

0.040 ohms gives 6.15A peak.  This regulator regulates peak current to get average you need to do all the calculations for your design.  Is your inductor rated for the peak current you are trying to run.  It will need margin as well.  Is this a new design on a PCB or a modified board?

This device can support 6A loads if the circuit is designed for that.

As far as high current operation.  The P-channel MOSFET choice, switching frequency and input voltage will determine a few things.  At higher gate charge the VCC capacitor connection should move to CSN instead of Vin, see below from the datasheet:

"It is important to consider the gate charge of Q1. As the input voltage increases from a nominal voltage to its
maximum input voltage, the COFT architecture will naturally increase the switching frequency. The dominant
switching losses are determined by input voltage, switching frequency, and PFET total gate charge (Qg). The
LM3409/09HV must provide and remove charge Qg from the input capacitance of Q1 to turn it on and off. This
occurs more often at higher switching frequencies which requires more current from the internal regulator,
thereby increasing internal power dissipation and eventually causing the LM3409/09HV to thermally cycle. For a
given range of operating points the only effective way to reduce these switching losses is to minimize Qg.
A good rule of thumb is to limit Qg < 30nC (if the switching frequency remains below 300kHz for the entire
operating range then a larger Qg can be considered). If a PFET with small RDS-ON and a high voltage rating is
required, there may be no choice but to use a PFET with Qg > 30nC.
When using a PFET with Qg > 30nC, the bypass capacitor (CF) should not be connected to the VIN pin. This will
ensure that peak current detection through RSNS is not affected by the charging of the PFET input capacitance
during switching, which can cause false triggering of the peak detection comparator. Instead, CF should be
connected from the VCC pin to the CSN pin which will cause a small DC offset in VCST and ultimately ILED,
however it avoids the problematic false triggering.
In general, the PFET should be chosen to meet the Qg specification whenever possible, while minimizing RDS-ON.
This will minimize power losses while ensuring the part functions correctly over the full operating range."

Best Regards,

Hello Asif,

Here are the calculations for your design per the schematic:

toff = 2.28 us

dutynom = 77.8%  no losses included

inductor ripple = 1.14A  (it will actually be higher because the inductor you are using is going into saturation and is between 30-40% lower than the specification)

Ipeak = 6.57A

Ipeak for 40 mohm current sense resistor = 6.15A

Iaverage for 40 mohm current = 5.58A  (it will be lower due to the inductor saturation)

ton = 7.99 us

Fsw = 97 KHz

The MOSFET you are using is much too small.  0.30 ohms at 6A and 80% duty cycle is 8.6 watts of dissipation when the MOSFET is at 25C.  It will get worse as it heats.  It also will have a 1.8V drop across it when it is on (0.30 ohm * 6A) = 1.8V again at 25C.  On resistance will double when the MOSFET is at 150C.

The inductor may work but the calculations get more difficult and there may be current drift with temperature change.

Do the two boards with failed ICs also have the MOSFET damaged?  If the MOSFET gets damaged this way the IC will most like also fail.

The inductor should change, the MOSFET and the current sense resistor should change.  I don't know what the rest of the schematic looks like such as the freewheel diode, etc.

Best Regards,