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LM5118-Q1: Issue with running under load, and schematic review

Kieran Lee
Prodigy 70 points
Part Number: LM5118-Q1
Other Parts Discussed in Thread: LM5118

Hello,

I am having difficulty getting a 24VDC to 24VDC regulator working using the LM5118-Q1. It is to protect some equipment in an industrial automotive environment.

The specs I hope to achieve are:

VIN: 8-75V, 24V nominal.
VOUT: 24V
IOUT: 2A

Attached is the schematic and a picture of the board layout I would like to use. Could I please have someone more experienced comment on these designs to see if they are suitable? The design is based off a Webench design, with a few of the components tweaked and the footprint of the board reduced. 

Also, I have attempted to build the circuit on a breadboard using a breakout of the IC components. When the circuit has no load, it works as expected, however, connecting a 5-30Ohm resistor as a load causes the output to drop to 0.6V when the input is above ~12V, and varies widely when the input is below that. I intend to get a PCB made to replace the breadboard, but not before I have someone review the layout to point out any obvious errors that might be the reason the breadboard attempt doesn't work.

Thanks in advance.

Schematic:
 VregReworkSchem.pdf

Board Layout:
VregReworkBrd.pdf

  • 0
    TI__Mastermind 21720 points

    Hello Kieran,

    Thanks for reaching out with your questions and for using the LM5118.

    So far the only test that you have done are on the bread board correct? Due to noise it can be tricky to get a switching regulator to operate on a bread board. In order to review the layout can you please pint off a layer by layer PDF of the board?

    Thanks,

    Garrett

  • 0 in reply to Garrett Roecker
    Prodigy 70 points

    Hi Garrett

    It appears to me that the reply I tried to post hasn't appeared, so I'm trying again.

    Here are the layer by layer PDFs of the board.

    8357.VregReworkTopLayer.pdf

    3515.VregReworkBottomLayer.pdf

    8585.VregReworkTopSilk.pdf


  • 0 in reply to Kieran Lee
    TI__Mastermind 21720 points

    Hi Kieran,

    The schematic looks okay. I don't see anything that sticks out as being incorrect.

    On the lay out there are a few things that I recommend.

    1. High-side gate drive traces: The HO and SW traces should be routed side by side. The SW pin should connect directly to the source of the high-side MOSFET. This will minimize the gate driver current loop reducing the noise in the system.

    2. Ensure the CSG is routed to the current sense resistor and should be routed close to the CS trace. The CSG and CS pins should form a Kelvin connection to sense the resistor voltage.

    3. Minimize the high di/dt current loops. Basically minimizing the loops between the high side switch, input capacitors and the current sense resistor.

    4. Create an AGND polygon to use for noise sensitive signals such as the RT resistor, SS capacitor and feedback resistors. This should connect to the exposed pad through the AGND pin. This is where the PGND should be tied as well. Please see the LM5118 EVM for and example.

    Please also take a look at the LM5118 evaluation module for guidance. I recommend implementing a 4 layer design so that ground layers can be used to shield noise sensitive signals.

    Here is a link that goes over some general topics for SMPS layout.

    Thanks,

    Garrett

  • 0 in reply to Garrett Roecker
    Prodigy 70 points

    Thanks for your help and advice Garrett