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LMG3410R070: Layout Design with Single Layer

Brian Wang0928
Genius 14030 points
Part Number: LMG3410R070

Hello, 

My customer wants to explore the GaN technology for motor drive application. Regarding to the layout design consideration, customer would like to know if single layer PCB is ok when using the LMG3410Rxxx GaN, or not? RD just would like to know if there is any limitation or design consideration with LMG3410 on single PCB design. (Assume there is no heat problem). 

Regards

Brian

  • 0
    TI__Genius 16390 points

    Hello Brian,

    Generally speaking, it’s not the best option to do the single layer PCB since it can’t do inductance cancellation and power loop minimization. However, if application requires one layer PCB, we have some general design rules in the link here: http://www.ti.com/lit/an/snoa946a/snoa946a.pdf. When one layer is used:

    To minimize the power loop for lowest parasitic inductance:

    • Place GaN device and bypass capacitor as close as possible.
    • Use multiple small ceramic bypass capacitors similar to our half-bridge EVM.
    • Reduce the trace length in the lateral power loop

    For better thermal performance it can also follow our general design rules as multi-layer board:

    • Larger area of thermal vias for heat dissipation
    • Reduce board thickness

    When the power loop is minimized, the voltage ringing can be reduced and GaN Fet will have a better slew rate, which allows applications to take advantage of GaN.

     

    Regards,

    Yichi Zhang