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BQ76940: 8KV air gap ESD fail

Part Number: BQ76940

Dear TI Experts,

My customer failed ESD test under 8KV air gap throught P+/P- pad, the phenomenon is regout no output.  BQ76940 can recover after reset, could you give some advices how to improve this?

Below is PCB layout. Thanks.

  • Hi Bruce,

    Thanks for the schematic, it is very helpful.

    As you know ESD behavior can be very dependent on the board.  In general you want the ESD to bypass the sensitive electronics and be carried to the large sink capacitance of the system, usually the cells.   Your P+, P-, B+, B- keeps the ESD currents from the pack terminals away from the electronics. With the currents going to the cells some could come back to the board from the cell taps.  Signals to the IC should go through the filter resistor and past the filter capacitor before reaching the IC pin.  You have that on the group of cell inputs from P1 through R8, past C6 to U1 for example.  With the BQ76940 this can be a challenge on the VC5X, VC10X and BAT pins because of the large power filter capacitors (C29, C30, C31), they tend to get put to the side of the IC and routing may not be preferred.  I cant see clearly from the diagram, you might check this.  It is also important to keep the capacitors which connect to VSS at the same potential both for DC (as shown in figure 20 of the data sheet) and the ESD current. In the layout it looks like that separation from the high current path is maintained, you will need to check if there is a separation which could be influenced by ESD.

    Since the REGOUT is off and a re-boot restores operation, it would appear the bottom cell group of the BQ76940 reset. This could be from a large transient on VC5X vs VSS at the IC.  Another cause could be the short of CAP1 which seems unlikely.  Another might be a pin  forced below VSS such as by more ESD coupling to one capacitor's VSS vs another's.  In your schematic there is no resistance between Q1 gate and the DSG pin, or D5 and the DSG pin.  This could allow a transient to push DSG below VSS possibly causing a reset.  A recent e2e user reported solving an ESD issue using 100 ohm between the DSG pin and the FETs.  They also added some capacitance between gate and source, the effect of that is not clear, it would slow switching some.   Some FET vendors will recommend a common gate resistor with smaller resistors between the individual gates to avoid oscillation during switching.

    Hope these comments and suggestions help.

  • Dear WM,

    Thank you so much for these detailed suggestions, we'll try these methods further.