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How much current can the low-side FET (leakage null control circuit) sink? Is there a current limit or saturation level?
2. Using the unencrypted PSpice model, when VIN > VOUT, and an external source drives current into the VOUT node, the IOUT is negative (current flow into OUT pin), the I_IN is also negative (current flow out of IN pin). Is it the correct behavior? How is it possible?
Hi Ding,
As the datasheet suggested, there is no internal current limit for reverse current from the output to the input.
2. Using the unencrypted PSpice model, when VIN > VOUT, and an external source drives current into the VOUT node, the IOUT is negative (current flow into OUT pin), the I_IN is also negative (current flow out of IN pin). Is it the correct behavior? How is it possible?
The simulator normally provides typical performance during a device's normal use. The way you set it up by having a voltage source higher than the output voltage may not be properly modeled. It's possible to have current flowing into the output of the LDO when you a 5-V voltage source at the 3.3V output. But if your Vin is at 10V, you should not see a negative I_out.
I would strongly suggest you get one of the EVM for this device to evaluate the performance if possible.
Regards,
Jason Song
