Other Parts Discussed in Thread: UCC28780
Hi,
I'm investigating a main switch failures on a flyback converter with active clamp topology. I'm are seeing an event where the output gate signal of the UCC2893 does a kind of hiccup or double pulse whenever the sync signal gets close to the falling edge of the first gate pulse.
The IC bias is around 10V and had been previously stablished. The sync frequency is around 186 KHz and the programmed frequency on the IC is 85Khz.
The outputs of the PWM IC are connected to a high side/low side driver IC IRS21867S to drive both low and high side mosfets. I have disabled the high side mosfet signal so only the low side mosfet is switching ON/OFF while the intrinsic diode of the high side mosfet is working in conjunction with the RC in the clamp circuit.
CH1 (yellow) is the signal applied directly to the gate of the low side mosfet Q14 and it has about 200nS delay from the gate signal coming out of the PWM IC (CH4-green). SYNC pulse is on CH7 (pink) while Q14 VDs is on CH3 (red).
I've captured more events where whenever the sync pulse falls close to the falling edge of the main fet gate signal it causes a double pulses increasing the frequency up to more than 1MHz. The peak current on the second pulse gets higher and after that it seems to go back to normal.
We apply the sync pulses at a fixed frequency and once the PWM bias has been stablished. We also enable the high side mosfet at the same time, although on this case the gate signal top the high side fet has been disconnected for the purpose of investigation and the gate to source terminals have been shorted to prevent any undesired triggering.
Is there a reason why the PWM triggers this double pulse behavior whenever the sync pulse falls close to the falling edge of the main gate pulse?
