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BQ76200: Pre-discharge driving high side fets in BMS

Sebastian de Leon
Prodigy 190 points
Part Number: BQ76200
Other Parts Discussed in Thread: BQ76940, TIDA-010030,

Hi,

I'm studying ref design TIDA-010030 (13s BMS based on BQ76940 with high side fet drivers and gauge). It implements a pre-discharge path with 300 ohms bleeding resistor in parallel to the discharge FET. I saw this before in other BMS boards, even with much smaller resistor values.

I read the datasheets, and understood that this is useful for discharging a high capacitive load for detecting load removal, to reestablish the system in case of a fault..

1. In the circuit, I can't understand the current path, when activating the pre discharge fet, that will discharged a capacitor in the load. How is it works?

2. When should I activate the fet? Only in case of SCD or OCD before I try to activate FETs again? Should I sense in that case PACK+ terminal through TIDA-010030 waiting for a condition? What would be that condition?

I'm sorry about these questions, I really tried to figure them out and still can't understand it.

Kind regards. 

  • 0
    Prodigy 190 points

    sebastian de leon said:

    2. When should I activate the fet? Only in case of SCD or OCD before I try to activate FETs again? Should I sense in that case PACK+ terminal through TIDA-010030 waiting for a condition? What would be that condition?

    I meant, through BQ76200

    K.R

  • 0 in reply to Sebastian de Leon
    TI__Guru 54715 points

    Hi Sebastian,

    1. The thought is that the system has a large capacitance at its input and some circuit which may discharge it over time.  When the battery is connected and tries to turn on that capacitance looks like a short circuit and can cause a fault in the battery.  The pre-discharge circuit allows the battery to charge the capacitance to prevent short circuit at turn on of the DSG. It can also be used as a test current to see if a short is still present, which seems to be the use in the picture at figure 27 of the TIDA-010030 design guide. 

    Looking at the TIDA-010030 schematic, page 4, when the MCU sets PDCHG high Q21 turns on pulling PDCHG_G down below the source (PDCHG_S).  On page 2 this will turn on Q31 P-channel FET.  Q30 is a diode if off, or a low resistance if on.  Current will flow from BAT+ through the fuse, Q30, Q31 and the R132-R133 combination to Pack+ to charge the capacitance in the load.  With the values in the schematic the time constant will be essentially 302 ohms x the load capacitance.

    2. Figure 27 of the design guide seems to show using the pre-discharge as a test to see if it is OK to turn on the FET.  That can be a good use.  As shown in the figure with no load the Pack+ voltage ramps up quickly.  If the system had a 1000 uF input capacitance the time constant would be (302 x 1000) uS = 0.3 seconds. In a short test such as figure 27 the voltage may not rise much.  You would need to decide if you make a decision based on a small voltage rise or if you leave the pre-discharge path on for longer time to restore the voltage closer to normal.  Realize that if the system provides a load the current will be limited by the R132-R133 combination.  In general you would want to use the pre-discharge any time you turn on the discharge FET, after OCD and SCD as you indicate, but also after UV, OT, UT, or just on start up.  The algorithm you use will depend on your system needs.