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TPS24751: Pspice model and turn on and off delays

Part Number: TPS24751

Good afternoon I'm trying to simulate the component during an overvoltage. the overvoltage threeshold is set at 5.5V.

As soon as the voltage rise above that level I'd expecting to see a small delay before the circuit opening caused by the 11mA charge pump which discharge the gate (chap 9.3.4 of the datasheet) and 1us of deglitch time.

In reality there is no delay between the two signals as you can see from the picture:

V(V3) is the voltage on pin Overvoltage

I(Rload) is the output current

is this feature not modelled? is it the same also for the ciruit breaker functionality?

Thank you

TPS24751_Overvoltage.zip

  • Hi Alberto,

    I will check and get back before Friday.

    Best Regards,

    Rakesh

  • Hi Alberto,

    To reduce the simulation time, most of the blocks are realized using logic components rather than the equivalent analog nature. It looks the model is developed with care to show the functional operation of the device and the delays are not properly taken care. Please let us know if this is a major concern.

    Best Regards, Rakesh

  • I'm sorry, but i need to understand the "let through" energy of this device in case of overvoltage and overcurrent.

    Do you think it would be possibile to provide a model with turn off delays (overvoltage and ovecurrent) in a reasonable time?

    Thank you

  • Hi Alberto,

    GATE is discharged by 11mA sink during OV event and 1A for circuit breaker event. Considering 4nF GATE capacitance (Figure 25), the GATE will be discharged in <5us for OV event and <200ns for circuit breaker event. These time intervals does not cause stress on the MOSFET. 

    Is the above answers your question. ? I will keep this model update in pipeline to our modelling team, but it may take some time due to other priorities. 

    Best Regards, Rakesh