TLC59581: GCLK Calculation and Adjusting Frame Rate

Hi David,

    Yes. The GCLK is too high for 16bit, 8 scan at 120 Hz frame rate.

    You can configure PWM resolution from 8bit to 16bit. The TLC59581 can support 32-multiplexing(maxium), which is depend on the capacity of SRAM.

Hi Charles,

Thanks for the response! What about the use of the FC2 bit on SEL_GCLCK_EDGE?

Would this let us reduce the number of GCLK cycles in half?

We'd like to get a 8x 48 array at 60fps if possible, can you clarify what mean by we can only support a max of 32 multiplexing?

Thanks,

David

Glad to here that I can alter the resolution of the PWM.  However, none of the documentation that I've seen says or even implies how that might be done.  Can you point me to the required information?

Hi David,

    As I mentioned above, the TLC59581 can support 32-multiplexing(maxium), which is depend on the capacity of SRAM.

Yes, I have read that document.  It implies that I must output 256*<num_rows> blocks of 257 GCLKs for the 8x8 mode and doesn't suggest any way of reducing this total number.  Of course, I can switch to the 7x9 mode, but that doesn't really gain me anything.  

I may be missing something, but I don't know what.  I'm trying to get the GCLK frequency down to 16MHz.  My need is 120fps x 8 lines x 257 x 256 which is what is required to output 16bit PWM.  Of course, I don't really need 16 bits, 12 bits would be fine.  I just don't see any documentation on reducing the output to 12 bits in either the data sheet or the document that you reference.

So do I output segments of 257 GCLKs x 16 segments or do I output 17 GCLKs x 256 segments to get 12 bits?  I'm assuming the former since it is 257 x 256 to get 16 bits.

Thanks for the clarification.

Hi Thomas, David,

     Do you have any more questions?

Just this: What effect does the use of the FC2 bit SEL_GCLCK_EDGE have on the required number of GCLKS? (I suspect that it divides the number in half somehow since it allows the output state to change twice per clock, but does it reduce the number of sub periods or does it change the required clocks in each period?)

Charles-Chen said:

Hi Thomas,

    The number of GCLK will reduced to half if SEL_GCLK_EDGE=1.

Ok, thanks for that information.  Now for the follow up: would this reduce the number of GCLK cycles per sub segment (i.e. from 257 to 129) or reduce the number of sub segments?