Hi Team,
My customer reports a problem with TPS54340. In their application ckt, to synchronize the DC/DC to system clock, they connect a system clock from a FPGA pin to RT/CLK pin of TPS54340 through a 0.1uF cap. While in some conditions they found the synchronization is unnecessary, in those conditions they keep the 0.1uF cap on board but disable the FPGA clock out, the corresponding FPGA pin is set in high-Z condition. The problem is in such kind of conditions, some device cannot keep stable, until the 0.1uF cap is removed. Why? If the cap on RT/CLK pin is not allowed?
Thank you!
John
