LM5112-Q1: Spice model syntax error

Alexander Skulsky

Intellectual 270 points

Part Number: LM5112-Q1
Other Parts Discussed in Thread: LM5112, TINA-TI

I am trying to use LM5112 spice model in Keysight ADS but it sais it has a syntax error.

I read in one of the threads here that it is due to bad translation off switch models in ADS.

can you provide an updated model for ADS, please

over 5 years ago

0 Mamadou Diallo over 5 years ago

TI__Genius 13445 points

Hello Alexander,

Can you please share the thread where you read about the bad translation off the switch models so that I can follow up from there. Was that thread referring to to this driver specifically?

Can you also confirm that you're using the Unencrypted PSpice model?

Regards,

-Mamadou

0 Alexander Skulsky over 5 years ago in reply to Mamadou Diallo

Intellectual 270 points

Hello Mamadou

this is the link where I read it:

https://e2e.ti.com/support/tools/ccs/f/81/t/112689?-Syntax-Error

I am able to import the model but when I try to simulate it sais there is a syntax error in line 29

Yes, I have downloaded the unencrypted PSpice model

Thanks

0 Mamadou Diallo over 5 years ago in reply to Alexander Skulsky

TI__Genius 13445 points

Hello Alexander,

Thanks for the link. It sounds like the code still runs on the link you've shared, is that also the case for you?

Can you please share the code on line 29?

Meanwhile I will review the PSpice model and get back to you soon.

Regards,

-Mamadou

0 Alexander Skulsky over 5 years ago in reply to Mamadou Diallo

Intellectual 270 points

Hello

this is the error I get in ADS

and I have attached the netlist

Fullscreen netlist.cnex.txt Download

*

.subckt DMC1030UFDB_lib:DMC1030UFDB:schematic N_D N_G N_S P_D P_G P_S  _M=1
CCGD P_node13 P_node14 C=9.5e-10 M $.model $W $L
CCGS P_node2 P_node3 C=7.966e-10 M $.model $W $L
DD1 P_node13 P_node12 DLIM m
DD2 P_S P_node15 DLIM m
DDDG P_node14 P_node15 DCGD m
DDSD P_D P_node3 DSUB m
MM1 P_node1 P_node2 P_node3 P_node3 PMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m
CPage1_CGD _node13 _node14 C=1.22e-09 M $.model $W $L
CPage1_CGS _node2 _node3 C=8.902e-10 M $.model $W $L
DPage1_D1 _node12 _node13 DLIM m
DPage1_D2 _node15 0 DLIM m
DPage1_DDG _node15 _node14 DCGD m
DPage1_DSD _node3 N_D DSUB m
MPage1_M1 _node1 _node2 _node3 _node3 NMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m
RPage1_R1 _node13 0 1 M $.model $W $L
RPage1_R2 _node12 _node15 1 M $.model $W $L
RPage1_RD N_D _node1 0.01313 M $.model $W $L
RPage1_RG N_G _node2 1.63 M $.model $W $L
RPage1_RS N_S _node3 0.001 M $.model $W $L
RR1 P_node13 P_S 1 M $.model $W $L
RR2 P_node12 P_node15 1 M $.model $W $L
RRD P_D P_node1 0.03274 M $.model $W $L
RRG P_G P_node2 4.88 M $.model $W $L
RRS P_S P_node3 0.001 M $.model $W $L
.ends DMC1030UFDB_lib:DMC1030UFDB:schematic

.subckt LM5112_TRANS_lib:LM5112:schematic IN IN_B IN_REF VCC OUT VEE  _M=1
CC_C1 VEE OUT C=1.4e-09 M $.model $W $L
xX_U12 N14862041 N14869697 N14859687 IN_REF LM5112_TRANS_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08
xX_U13 N14861648 N14869610 N14859687 IN_REF LM5112_TRANS_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08
xX_U16 N14859687 N14862041 IN IN_REF LM5112_TRANS_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4
xX_U17 N14859687 N14861778 IN_B IN_REF LM5112_TRANS_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4
xX_U18 N14875621 IN_REF N14860433 VEE LM5112_TRANS_lib:LS_BASIC_GEN:schematic m=1
xX_U21 N14861778 N14861648 N14859687 IN_REF LM5112_TRANS_lib:INVERTER_BASIC_GEN:schematic m=1 VTHRESH=6
xX_U22 N14869787 N14869697 N14869610 N14875621 N14859687 IN_REF LM5112_TRANS_lib:NAND3_BASIC_GEN:schematic m=1 VTHRESH=6
xX_U3 N14859687 N14869787 VCC IN_REF LM5112_TRANS_lib:UVLO_BASIC_GEN:schematic m=1 VTHRESH=3 VHYST=0.23
xX_U8 VCC OUT N14860433 VEE LM5112_TRANS_lib:VSW_BASIC_GEN:schematic m=1 RON=2 ROFF=1000000 VON=0.1 VOFF=6
xX_U9 OUT VEE N14860433 VEE LM5112_TRANS_lib:VSW_BASIC_GEN:schematic m=1 RON=0.857 ROFF=1000000 VON=6 VOFF=0.1
.ends LM5112_TRANS_lib:LM5112:schematic

.subckt LM5112_TRANS_lib:INVERTER_BASIC_GEN:schematic IN OUT VCC VSS  _M=1 VTHRESH=2.5
.ends LM5112_TRANS_lib:INVERTER_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:NAND3_BASIC_GEN:schematic IN1 IN2 IN3 OUT VCC VSS  _M=1 VTHRESH=2.5
.ends LM5112_TRANS_lib:NAND3_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:UVLO_BASIC_GEN:schematic SUPPLY OUT CN+ CN-  _M=1 VTHRESH=2.5 VHYST=0.5
.ends LM5112_TRANS_lib:UVLO_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:LS_BASIC_GEN:schematic ND+ ND- LS+ LS-  _M=1
.ends LM5112_TRANS_lib:LS_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:VSW_BASIC_GEN:schematic ND1 ND2 CN+ CN-  _M=1 RON=1 ROFF='1e+6' VON=3 VOFF=2
.ends LM5112_TRANS_lib:VSW_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:BUF_DELAY_BASIC_GEN:schematic IN OUT VCC VSS  _M=1 VTHRESH=2.5 DELAY='1e-8'
CC1 _node4 VSS C=DELAY*1.4 M $.model $W $L
RR1 _node3 _node4 1 M $.model $W $L
.ends LM5112_TRANS_lib:BUF_DELAY_BASIC_GEN:schematic

.subckt LM5112_TRANS_lib:INPUTHYST_BASIC_GEN:schematic SUPPLY OUT CN+ CN-  _M=1 VTHRESH=2.5 VHYST=0.5
.ends LM5112_TRANS_lib:INPUTHYST_BASIC_GEN:schematic

.subckt FET simulation_lib:cell_1:schematic 
DDIODE1 _net4 _net17 DIODEM1 m
RR2 0 _net17 1 M $.model $W $L
RR4 _net17 VDD 200 M $.model $W $L
VSRC4 VDD 0 4.2
xX3 _net4 _net4 _net4 _net4 _net4 _net4 DMC1030UFDB_lib:DMC1030UFDB:schematic m=1
xX4 DRIVE 0 0 VDD COM 0 LM5112_TRANS_lib:LM5112:schematic m=1
.ends FET simulation_lib:cell_1:schematic


.end

0 Mamadou Diallo over 5 years ago in reply to Alexander Skulsky

TI__Genius 13445 points

Hi ALexander,

Can you please share the .net netlist showing line 29. I ask because line 29 on the PSpice netlist from our model is a comment line.

Seeing exactly what line 29 looks like on the ADS code (after you import the model) will be helpful to figure out root cause.

Thanks.

-Mamadou

0 Alexander Skulsky over 5 years ago in reply to Mamadou Diallo

Intellectual 270 points

is this what you are looking for?

Fullscreen CNEX.log Download

Design Name: FET simulation_lib:cell_1:schematic
Date:        November 22, 2019 21:23:01


WARNING! Instance EGD of type ads_datacmps:SDD2P does not have a netlisting definition.
WARNING! Instance FFB of type ads_datacmps:SDD1P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance Page1_EGD of type ads_datacmps:SDD2P does not have a netlisting definition.
WARNING! Instance Page1_FFB of type ads_datacmps:SDD1P does not have a netlisting definition.
WARNING! Instance Page1_NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance Page1_VFB of type ads_sources:VtUserDef does not have a netlisting definition.
WARNING! Instance VFB of type ads_sources:VtUserDef does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance V_V1 of type ads_sources:VtUserDef does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD4P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD6P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD3P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD2P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance S1 of type ads_rflib:spice_vswitch does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD4P does not have a netlisting definition.
WARNING! Instance E2 of type ads_datacmps:SDD4P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance E1 of type ads_datacmps:SDD3P does not have a netlisting definition.
WARNING! Instance NetlistInclude0 of type ads_simulation:NetlistInclude does not have a netlisting definition.
WARNING! Instance SRC5 of type ads_sources:VtPulse does not have a netlisting definition.

Netlisting finished at 21:23:03

Fullscreen 6403.netlist.cnex.txt Download

*

.subckt DMC1030UFDB_lib:DMC1030UFDB:schematic N_D N_G N_S P_D P_G P_S  _M=1
CCGD P_node13 P_node14 C=9.5e-10 M $.model $W $L
CCGS P_node2 P_node3 C=7.966e-10 M $.model $W $L
DD1 P_node13 P_node12 DLIM m
DD2 P_S P_node15 DLIM m
DDDG P_node14 P_node15 DCGD m
DDSD P_D P_node3 DSUB m
MM1 P_node1 P_node2 P_node3 P_node3 PMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m
CPage1_CGD _node13 _node14 C=1.22e-09 M $.model $W $L
CPage1_CGS _node2 _node3 C=8.902e-10 M $.model $W $L
DPage1_D1 _node12 _node13 DLIM m
DPage1_D2 _node15 0 DLIM m
DPage1_DDG _node15 _node14 DCGD m
DPage1_DSD _node3 N_D DSUB m
MPage1_M1 _node1 _node2 _node3 _node3 NMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m
RPage1_R1 _node13 0 1 M $.model $W $L
RPage1_R2 _node12 _node15 1 M $.model $W $L
RPage1_RD N_D _node1 0.01313 M $.model $W $L
RPage1_RG N_G _node2 1.63 M $.model $W $L
RPage1_RS N_S _node3 0.001 M $.model $W $L
RR1 P_node13 P_S 1 M $.model $W $L
RR2 P_node12 P_node15 1 M $.model $W $L
RRD P_D P_node1 0.03274 M $.model $W $L
RRG P_G P_node2 4.88 M $.model $W $L
RRS P_S P_node3 0.001 M $.model $W $L
.ends DMC1030UFDB_lib:DMC1030UFDB:schematic

.subckt FET simulation_lib:LM5112:schematic IN IN_B IN_REF VCC OUT VEE  _M=1
CC_C1 VEE OUT C=1.4e-09 M $.model $W $L
xX_U12 N14862041 N14869697 N14859687 IN_REF FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08
xX_U13 N14861648 N14869610 N14859687 IN_REF FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08
xX_U16 N14859687 N14862041 IN IN_REF FET simulation_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4
xX_U17 N14859687 N14861778 IN_B IN_REF FET simulation_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4
xX_U18 N14875621 IN_REF N14860433 VEE FET simulation_lib:LS_BASIC_GEN:schematic m=1
xX_U21 N14861778 N14861648 N14859687 IN_REF FET simulation_lib:INVERTER_BASIC_GEN:schematic m=1 VTHRESH=6
xX_U22 N14869787 N14869697 N14869610 N14875621 N14859687 IN_REF FET simulation_lib:NAND3_BASIC_GEN:schematic m=1 VTHRESH=6
xX_U3 N14859687 N14869787 VCC IN_REF FET simulation_lib:UVLO_BASIC_GEN:schematic m=1 VTHRESH=3 VHYST=0.23
xX_U8 VCC OUT N14860433 VEE FET simulation_lib:VSW_BASIC_GEN:schematic m=1 RON=2 ROFF=1000000 VON=0.1 VOFF=6
xX_U9 OUT VEE N14860433 VEE FET simulation_lib:VSW_BASIC_GEN:schematic m=1 RON=0.857 ROFF=1000000 VON=6 VOFF=0.1
.ends FET simulation_lib:LM5112:schematic

.subckt FET simulation_lib:INVERTER_BASIC_GEN:schematic IN OUT VCC VSS  _M=1 VTHRESH=2.5
.ends FET simulation_lib:INVERTER_BASIC_GEN:schematic

.subckt FET simulation_lib:NAND3_BASIC_GEN:schematic IN1 IN2 IN3 OUT VCC VSS  _M=1 VTHRESH=2.5
.ends FET simulation_lib:NAND3_BASIC_GEN:schematic

.subckt FET simulation_lib:UVLO_BASIC_GEN:schematic SUPPLY OUT CN+ CN-  _M=1 VTHRESH=2.5 VHYST=0.5
.ends FET simulation_lib:UVLO_BASIC_GEN:schematic

.subckt FET simulation_lib:LS_BASIC_GEN:schematic ND+ ND- LS+ LS-  _M=1
.ends FET simulation_lib:LS_BASIC_GEN:schematic

.subckt FET simulation_lib:VSW_BASIC_GEN:schematic ND1 ND2 CN+ CN-  _M=1 RON=1 ROFF='1e+6' VON=3 VOFF=2
.ends FET simulation_lib:VSW_BASIC_GEN:schematic

.subckt FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic IN OUT VCC VSS  _M=1 VTHRESH=2.5 DELAY='1e-8'
CC1 _node4 VSS C=DELAY*1.4 M $.model $W $L
RR1 _node3 _node4 1 M $.model $W $L
.ends FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic

.subckt FET simulation_lib:INPUTHYST_BASIC_GEN:schematic SUPPLY OUT CN+ CN-  _M=1 VTHRESH=2.5 VHYST=0.5
.ends FET simulation_lib:INPUTHYST_BASIC_GEN:schematic

.subckt FET simulation_lib:cell_1:schematic 
DDIODE1 _net4 _net17 DIODEM1 m
RR2 0 _net17 1 M $.model $W $L
RR4 _net17 VDD 200 M $.model $W $L
VSRC4 VDD 0 4.2
xX3 _net4 _net4 _net4 _net4 _net4 _net4 DMC1030UFDB_lib:DMC1030UFDB:schematic m=1
xX4 _net16 _net1 _net13 _net15 _net5 _net2 FET simulation_lib:LM5112:schematic m=1
.ends FET simulation_lib:cell_1:schematic


.end

0 Mamadou Diallo over 5 years ago in reply to Alexander Skulsky

TI__Genius 13445 points

Hello Alexander,

Thanks.

It looks the error occurs on the line of code below:

"xX_U12 N14862041 N14869697 N14859687 IN_REF FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08" please confirm.

I don't currently see the syntax error associated with that line of code along with the "FET simulation_lib:LM5112:schematic" sub-circuit but I am will further look into and get back to you within 24 to 48hrs.

Regards,

-Mamadou

0 Mamadou Diallo over 5 years ago in reply to Mamadou Diallo

TI__Genius 13445 points

Hello Alexander,

I have not seen any specific issues with the model for LM5112, I will advise to run the simulation in either PSpice and/or TINA_TI and let us know if you run into issues on those platforms.

I have copied some links that you might find useful when converting our unecrypted models to other simulation tools.

https://e2e.ti.com/support/tools/sim-hw-system-design/f/234/t/692613

As we cannot guarantee that our unencrypted models will work with other simulation tools outside of PSpice and TINA-TI, feel free to work with Keysight/Agilent to resolve the error in ADS as they will be more knowledgeable about their simulation platform.

I will mark this thread as "resolved" but feel free to let us know if you have issues running the model on PSpice and/or TINA-TI or if you have any gate drivers related questions.

Regards,

-Mamadou

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LM5112-Q1: Spice model syntax error