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BQ40Z80: ASCD test and DSG MOS burn

Lin daphne
Prodigy 50 points
Part Number: BQ40Z80

Hello there!

I was doing short circuit tests and came across a problem. When the MOS goes back to normal mode, since P+ & P- remain in short circuit state, DSG MOSFET burns out. Also, as far as I know, ASCD is fine. I want to ask that is there a way to make bq40z80 stop from going into recovery mode and only recover when charging(like CUV_RECOV_CHG).

Thanks!

  • 0
    TI__Guru* 76230 points

    hi Lin

    To prevent the device from tripping again, the condition that cause the safety condition has to be removed. You can set the conditions for recovery to be very far off from the condition that trips the fets to prevent it from retripping. Ps see the conditions in the TRM.

    thanks

    Onyx

  • 0
    TI__Mastermind 34745 points

    Hi Lin,

    There's a latch feature that prevent FETs from toggling ON and OFF continuously during a persistent fault condition. Please refer to the the TRM as Onyx mentioned.

    See pages 22 and 24 sections 3.7 and 3.7.3.

    http://www.ti.com/lit/ug/sluubt5b/sluubt5b.pdf

    3.7 Hardware-Based Protection The BQ40Z80 device has three main hardware-based protections—AOLD, ASCC, and ASCD1,2—with adjustable current and delay time. Setting AFE Protection Configuration[RSNS] divides the threshold value in half. The Threshold settings are in mV; therefore, the actual current that triggers the protection is based on the RSENSE used in the schematic design. In addition, setting the AFE Protection Configuration[SCDDx2] bit provides an option to double all of the SCD1,2 delay times for maximum flexibility towards the application's needs. For details on how to configure the AFE hardware protection, refer to the tables in Appendix A. All of the hardware-based protections provide a Trip/Latch Alert/Recovery protection. The latch feature stops the FETs from toggling on and off continuously on a persistent faulty condition. In general, when a fault is detected after the Delay time, the CHG and DSG FETs will be disabled (Trip stage), and an internal fault counter will be incremented (Alert stage). Since both FETs are off, the current will drop to 0 mA. After Recovery time, the CHG and DSG FETs will be turned on again (Recovery stage). If the alert is caused by a current spike, the fault count will be decremented after Counter Dec Delay time. If this is a persistent faulty condition, the device will enter the Trip stage after Delay time, and repeat the Trip/Latch Alert/Recovery cycle. The internal fault counter is incremented every time the device goes through the Trip/Latch Alert/Recovery cycle. Once the internal fault counter hits the Latch Limit, the protection enters a Latch stage and the fault will only be cleared through the Latch Reset condition. The Trip/Latch Alert/Recovery/Latch stages are documented in each of the following hardware-based protection sections. The recovery condition for removable pack ([NR] = 0) is based on the transition on the PRES pin, while the recovery condition for embedded pack ([NR] = 1) is based on the Reset time.

    3.7.3 Short Circuit in Discharge Protection The BQ40Z80 device has a hardware-based short circuit in discharge protection with adjustable current and delay. Additionally, this protection feature can be enabled to also create a PF by setting the [ASCDL] bit in Enabled PF B register.

  • 0 in reply to Damian Lewis
    Prodigy 50 points

    Hi Lewis,
    Thanks for replying. Unfortunately, this solution does not meet my requirements, since I cannot use PF and my [NR] = 1.
    Below is my probe picture.

    I have 5S cell battery and 3 parallel DSG MOS.
    When I do ASCD test manually, everything is fine. But if it remains in short circuit, this type of wave occurs(in the above picture).
    Do you have a solution to my problem or any suggestions for bypassing this issue?

  • 0 in reply to Lin daphne
    TI__Mastermind 34745 points

    Hi Lin,

    Do you have a schematic that you can share? It looks like the DSG FET turned back on due to recovery condition being met by it turning off, but it stays on even when current exceeds ASCD threshold. It should be toggling on and off.  Can you capture the DSG FET gate voltage during your test? It looks like the current is getting upto 150A. Is that correct? What is the size of your sense resistor? Do you know if the SRP or SRN pin getting damaged also? What is your ASCD threshold set to? My suspicion is that the DSG FET isn't turning off fast enough causing damage. WIth 3 parallel FETs, the gate capacitance can be high and as a result increase the FETs turn-off time. You can try reducing the gate to source resistor, but it will also increase your turn on time and reduce the gate drive voltage.