TPS40057: SS capacitor

Hi,

Please see 7.3.5 in datasheet. Equation 5 limits the minimum SS cap.

Hi Neal,

The Equation 5 is the limitation of minimum. (Equation 5 shows Tstart should be greater than the L-CO time constant.)

I would like to know the maximum limitation of SS capacitor. Of course, the customer should estimate the SS capacitor(SS time) that does not flow much current.

But we would like to know if there is the limitation of maximum SS time for this device.

Best Regards,

Koji Hamamoto

Hi Koji,

There is no max limitation.

Only note that, if the soft start time is long, when over current happens, during hiccup, the IC will sleep for long time without responding when the load becomes normal.

"seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this period. " See 7.3.3 for details.

Hi Neal,

Thank you for your support. 

You are correct. Equation 5 shows the minimum tStart.

And we have such a issue that Vout does not recover at some samples after released the OC. (Please see the following waveform)

SS cap ; 33nF

Time Div; 200ms/dic

Ch1(yellow); Vin 5V/div, Ch2(blue); Vout 1V/div

(For some samples , this phenomenon does not appear. Vout does recover after OC released and there are OCP behavior.)

As you mentioned, the long SS time affect the OC behavior.(IC will sleep for long time.)

So in this case, how can we calculate the maximum SS time(tStart) which does not happen that sleep behavior?

(Equation 5 can be calculated only the min tStart.)

Best Regards,

Koji Hamamoto

Hi neal

I have another result that shows this phenomenon.

We measured with the large load current such as more than 20A. Then this phenomenon(issue) has been reproduced on TI-EVM(TPS40055EVM).

Please see the following waveform.

>Board condition: (The some components are changed from default on TI-EVM.)

L1 changed to the inductor has large Isat more than 30A.

Css changed to 33nF .

> CH2: Vout, CH3: SS, CH4: Iout

SS keeps this level.

And I have some question.

1) At the abnormal behavior (above waveform), SS does not go down until 0V. Is this normal? (at this time , Css is 33nF)

2)On the datasheet, it mentions about SS.

  "The output voltage begins to rise when VSS/SD is SS/SD 6 I approximately 0.85 V."

   At OCP event, Vss need to go down bellow 0.85V for "7 soft start cycle" mode?

3)Does it go into this event (7 soft start cycle) even in case of Vss does not go down bellow 0.85V?

Could you give us any advice if you have any comment ?

Best Regards,

Koji Hamamoto

Hi, 

These questions are quite related to the inside design. Please send email to me. neal-zhang@ti.com

Hi Neal,

Thank you for your suggestion. I think it better to discussion about this issue with email.

I have some further information like schematic and waveform so I will send you these data as well.

Best Regards,

Koji Hamamoto