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Original question:

TPS65268-Q1: TPS65268-Q1, enable, disable

TPS65268-Q1: SW pin negative pulse is very big

Amelie Zheng
Genius 10865 points
Part Number: TPS65268-Q1

Hi Team,

My customer use the TPS65268-Q1 and found that the SW pin negative pulse is  very big.

1）DDR=1.5V

2）VDDARM-1.37V

3）3.3VK

At present, no obvious problems have been found in the schematic diagram.

In layout, Vin and input capacitor are placed in the bottom layer; inductance and output capacitor are placed in the top layer. Input power loop is long, and it may be one of the reasons.

In addition, when adding RC to the ground (10R+1nF)  in SW PIN , and no significant improvement was found.

Please help to confirm the problem, thank you!

  • 0
    TI__Expert 7500 points

    Hi Amelie,

    Firstly, it is one of reason for SW large ringing that if the Vin capacitor is placed in the bottom layer. We strongly recommend Vin cap is placed in the top layer and close to Vin pin.

    And for the waveforms, I have two questions:

    1. Why waveform2 VDDARM-1.37V SW rising edge doesn't have ringing?

    2. Please zoom in the rising and falling edge for waveform1 and 3. And when you capture the SW ring, please use smallest GND loop like below.

    Thanks,

    Lishuang

  • 0 in reply to Lishuang Zhao
    TI__Genius 10865 points

    Hi Lishuang,

    Thanks for your reply.

    As for the measurement, I also confirm with customer that they use the same smallest GND loop to test.

    I will ask customer to offer zoom in the rising and falling edge for waveform1 and 3. 

    I also don't know why waveform2 VDDARM-1.37V SW rising edge doesn't have ringing..

    May I ask do you have some common method to reduce the rising?For example:

    1) add serial res in BST PIN (BOOST)

    2) add RC in SW PIN

    3) add RL in Vin: 

    I can ask customer to have a try whether it works.

    How can I prove the main reason is Vin cap is on the bottom? (add another closer cap in Vin to prove?)

    Thanks!

  • 0 in reply to Amelie Zheng
    TI__Expert 7500 points

    Hi Amelie,

    The three methods above are all common method. And one added is that careful PCB layout to minimize the parasitic loop inductance in circuit. You can find in the below link on the bottom of page 5. And you can also find the comparison between input cap in top and bottom layer in page 8.

    http://www.ti.com/lit/an/slpa010/slpa010.pdf?keyMatch=RINGING%20REDUCTION%20TECHNIQUES%20FOR%20NEXFETTM%20HIGH%20PERFORMANCE%20MOSFETS&tisearch=Search-EN-everything

    Yes, if the customer can put the input cap in top layer and close to Vin, it is the best.

    Thanks,

    Lishuang

  • 0 in reply to Lishuang Zhao
    TI__Genius 10865 points

    Hi Lishuang,

    My customer has tried the three method and the application's method, and have no improvement about the negative pulse.

    Any other advice or suggestions? Thanks ！

    When zooming in, the waveform is as following:

    1.37V

    1,5V

    3.3V

  • 0 in reply to Amelie Zheng
    TI__Expert 7500 points

    Hi Amelie,

    The snubber burns the energy of the switch-node ringing. Please try some other Csnubber+Rsnubber combination. For example, 1nF+5Ohm, 1nF+0 Ohm, 500pF+5 Ohm. What's more, please add the snubber as close as possible to chip SW node and GND.

    If there is no improvement, please upload the layout.

    Thanks,

    Lishuang

  • 0 in reply to Lishuang Zhao
    TI__Genius 15135 points

    Hi, Amelie

    Agreed with Lishuang, in theory, RC snubber can alleviate the over spike voltage and under spike voltage on LX.

    Suggest to do the below test:

    1. set R=0ohm first, try C=1nF and 2.2nF.  

    2. in theory, the under voltage will be smaller at C=2.2nF, then keep C=2.2nF and try R=5ohm and 10ohm which should reduce the number of rings.

    Besides, why does the customer so care about the undershoot voltage on LX? Actually, I think this under voltage can be accepted.