WEBENCH® Tools/UC1845A-EP: Output Delay Discrepancy in PSPICE unencrypted model

Steve Widener

Part Number: UC1845A-EP
Other Parts Discussed in Thread: UCC28C45

Tool/software: WEBENCH® Design Tools

We are seeing a discrepancy in the PSPICE unencrypted model that does not agree with bench results. We have verified the UCC28C45 model has the same behavior.

The output duty cycle achieved in the spice model is nearly 50% given a sync pulse of ~70nsec and an oscillator frequency of ~ 684kHz. Actual measurements show a delay from the falling edge of the RTCT input pulse to the rising edge of the output of ~ 220nsec. This limits the achievable duty cycle. It appears this delay is not being properly modeled - please confirm.

Compare this to the measured signals :

Channel 1 is the output, Channel 3 is the RTCT input

COMP, FB, CS are all tied low with 10kohms. Vcc is 15V.

If you confirm this, can we update the models to include the delay to match the actual performance?

Thanks!

Steve

over 5 years ago

0 Teng Feng over 5 years ago

TI__Genius 13660 points

Hi Steve, please give a day to check this issue.—— Teng

0 Teng Feng over 5 years ago

TI__Genius 13660 points

Hi Steve,

Please see my simulation result, it also has a ~220ns delay. I think because your oscillator synchronization circuit is not same with datasheet's. It is not right.

Regards,

Teng

0 Steve Widener over 5 years ago in reply to Teng Feng

TI__Genius 11010 points

Thanks Teng.

For this application, we must have the sync signal driven in as I've shown - an FPGA will be applying a 0 - 3.3V pulse.

Is there something in the model that does not trigger the ~220nsec delay when a pulse is driven into RTCT? Do we have an equivalent circuit?

This mode of operation is shown in U-100A in Figure 23

http://www.ti.com/lit/an/slua143/slua143.pdf

0 Teng Feng over 5 years ago in reply to Steve Widener

TI__Genius 13660 points

Hi Steve,

Sorry for the delay response.

I also simulated using a digital logic input as an input to the RT/CT pin, there was no delay. and check datasheet, I couldn't find any place that can cause this delay.

So can you please share the actual measure circuit?

Maybe there is a testing issue, , because in the customer's simulation, they connect comp pin and CS pin to GND together, it may terminal the output of PWM comparator.

And I recommend to pull up COMP pin to VREF when testing.

Regards,

Teng

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WEBENCH® Tools/UC1845A-EP: Output Delay Discrepancy in PSPICE unencrypted model