TPS56637: Unclear points in layout recommendation

Takashi Onawa

Part Number: TPS56637

Hi Team,

I didn't understand what you want to tell us in following two sentences in datasheet, 10.1 Layout Guidelines. Can you supplement the details?

8. A separate VOUT path should be connected to the upper feedback resistor.
9. Make a Kelvin connection to the GND pin for the feedback path

Regards,

Takashi Onawa

over 5 years ago

0 Gerold Dhanabalan - Online Design Tools over 5 years ago

TI__Genius 14455 points

Hi Onawa-san,

For #8, In the layout image, it is asking you to have a trace to connect from the top feedback resistor to Vout. You can see the trace is shown as a dotted line in another layer.

For #9, it is recommending to make a short direct connection from the bottom feedback resistor to AGND as shown below. Have vias to connect to AGND plane as well.

Regards,

Gerold

0 Takashi Onawa over 5 years ago in reply to Gerold Dhanabalan - Online Design Tools

TI__Genius 13200 points

Hi Gerold-san,

Thanks for your prompt response on this.

Sorry I have two more question about the location and overlap between AGND and PGND, and about size reduction of the layout.

- Question regarding AGND layout

What layer should AGND be placed on?
Does it need to keep no pattern directly under AGND?
Or do all layers need to be AGND?

- Question regarding side reduction

In order to make it more smaller, Is it possible to delete this space from PGND of TOP layer?
Also, What it the estimated side effect due to the size reduction?

Regards,

Takashi Onawa

0 Takashi Onawa over 5 years ago in reply to Takashi Onawa

TI__Genius 13200 points

Hi Gerold-san,

Can I have some comments for my customer's questions above?

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Question about AGND

-----Just one layer is ok, recommend to make it adjacent to the components layer.

Question about PGND

-----Thermal will be impact, and loop from output GND to input GND will be impact a little as well, but it doesn't affect it work normally.

Yuchang

0 Takashi Onawa over 5 years ago in reply to Yuchang Zhang

TI__Genius 13200 points

Hi Yuchang-san,

Thanks for you comments.

>Just one layer is ok, recommend to make it adjacent to the components layer.

OK, I understand just one layer is enough.

One quick confirmation, Is it OK to put signal patterns and PGND to adjacent layer of AGND? In other words, should other upper and downer layers of AGND be left as void?

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Onawa-san,

Don't need making it void, just keep routing normally.

Yuchang

0 Takashi Onawa over 5 years ago in reply to Yuchang Zhang

TI__Genius 13200 points

Hi Yuchang-san,

Thanks, I understood about the AGND.

Sorry, let me ask one more questions about the sentence below.
This is one of our layout guide described in the datasheet(10.1 Layout Guidelines), However I didn't understand the meaning at all.

Which Vias do we need to take care? Or is this typo?

>3. Putting at least two vias for VIN and GND traces, and as close as possible to the pins

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Takashi-san

Just put some vias close to the VIN/GND pins to help thermal dissipation.

Yuchang

0 Takashi Onawa over 5 years ago in reply to Yuchang Zhang

TI__Genius 13200 points

Hi Yuchang-san,

Thanks for your prompt response.

OK, I understood it's just for thermal point of view for the GND.

What is VIN Via intended to be inserted for? Is this for the case which mid layer is used as power layer?

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Yes, your understanding is right, Takashi-san.

Yuchang

0 Takashi Onawa over 5 years ago in reply to Yuchang Zhang

TI__Genius 13200 points

Hi Yuchang-san,

OK, I understood. I think the layout guide is too less description to understood what you want. So I hope it will be improved in near future.

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Takashi-San, Thanks for suggestions, will ask team to pay attention about this.

Happy new year!

Yuchang

0 Takashi Onawa over 5 years ago in reply to Yuchang Zhang

TI__Genius 13200 points

Hi Yuchang-san,

Sorry, let me double check about Gerold's following replay in a first response of this thread.

9. Make a Kelvin connection to the GND pin for the feedback path.

>For #9, it is recommending to make a short direct connection from the bottom feedback resistor to AGND as shown below. Have vias to connect to AGND plane as well.

It looks the sentence describes about feedback path but his response is for ANGD connection. It doesn't make sense for me.

Regards,

Takashi Onawa

0 Yuchang Zhang over 5 years ago in reply to Takashi Onawa

TI__Mastermind 18510 points

Takashi,

I think maybe the description make you confusion, I think you can follow my words to route FB net,

FB resistor close to FB pin.

FB resistor's GND connect to AND pin, and AGND PIN connect to AGND plane with via

AGND plane connect to PGND plane with single point

For FB line, route it back after output cap from inner layer or bottom layer, refer to Ground plane, and away from switching noise source.

Follow above should be OK.

Yuchang

Power management

Power management forum

TPS56637: Unclear points in layout recommendation