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TPS3703-Q1: TPS3703-Q1 Glitch immunity to sensor pin at UV/OV

user5789841
Intellectual 305 points
Part Number: TPS3703-Q1

Hi Team，

     Actually I have 2 questions about glitch immunity to sensor pin at overvoltage and undervoltage:

        1.What does "overdrive[2.5%] above VIT+(OV)" mean in datasheet ? Is it mean we at least need reserve 2.5% voltage margin from VIT+(OV) for MCU's operation voltage? 

        2.I saw 2.5% margin is from VIT+(OV) at 25℃, how much margin we need to consider when the temperature at 125℃？

       

      For example :

          MCU Max operation voltage :5.5V

          Monitor chip:  TPS3703C7500DSERQ1   5V variant  7% accuracy

         so, VIT+(OV)=5*(1+7%)=5.35V   @ 25℃                                   if need 2.5% margin   ， V=5.35*(1+2.5%)=5.48V < Vmax_MCU=5.5V     OK

               VIT+(OV)=5*(1+7%+0.7%)=5.385V   @ 125℃                     if need 2.5% margin   ， V=5.385*(1+2.5%)=5.52V > Vmax_MCU=5.5V     NOK   ???

       Thanks!

        BR.

  • 0
    TI__Genius 11311 points

    Hi 

    2.5% overdrive is required to meet all the timing spec when you are giving faster ramp (in the range of 1V/us). If your ramp is slow or your timing is not very critical for you , then you can budget it with less overdrive also. 

    If you need to detect the fault within the timing spec limit and with high ramp rate then method 2 in your example is correct. 

       VIT+(OV)=5*(1+7%+0.7%)=5.385V   @ 125℃                     if need 2.5% margin   ， V=5.385*(1+2.5%)=5.52V > Vmax_MCU=5.5V     NOK   ???

     

    Regards

    Trailokya