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WEBENCH® Tools/TPS65263-Q1: Calculating reliable loop compensation values

Part Number: TPS65263-Q1
Other Parts Discussed in Thread: TPS65261, TPS65263, TPS65400

Tool/software: WEBENCH® Design Tools

Hi,

have inherited a design with this chip. It come with values, for compensation networks, that semt well working.

In order to assess this, i tried to simulate in webench the similar TPS65261 part , but probably due to my inexperience with webench could not be able to set the Output voltages needed, one of wich (5V) much higher than default one(0.9V). As i tried, webench kicked me out saying it can not find  non better specified component(s).

Anyway with default output voltages webench gave Rc and associated Caps values next to mine. But it appears not to be there a linear proportion, neither inverse, between Rc and Out voltages so can not infere CH1 Rc (and caps) value from webench suggestions.

Then I also wanted to try out the formulas given in 263 datasheet, using 1Mhz fck, 100khz Fc, and RL = V/expected max current; this for each branch.

Found Rc values are much higher than previous ones, hundreds kohms vs kohms. I tried these value sets in my HW and the control loops got all very unstable.

How can i calculate proper values then? Our designs are all digital, and experience rare steps in absorption and durable constant absorption intervals. By other hand, we need sourcing currents next to higher chip limits. So i guess i could advantage from slowing down the regulation response in order to limit the pwm jitter and avoid overcurrent thresholds tripping. 

Thanks for any suggestion

Francesco

  • Hi, Francesco

    1. Yes, you can use the TPS65261 bench to calculate compensation parameter.

    What is your specific application condition? I tried below condition, Webench works normally.

    Vin=12V, Buck1=5V, Buck2=0.9V, Buck3=1.8V.

    Maybe your problem is at Vin voltage range, suggest to change Vin and try again.

    2. In theory, the Rc and Vout should be linear proportion, which means we can use bigger Rc for big Vout. But at actual condition, Rc value is related crossover frequency fc, and affected by higher-order poles, they are not exactly linear proportion, they are only linear in certain fc range.  

    We cannot use very big Rc value, for tps65263x, based on my experience, suggest to set Rc smaller than 50 kohm when Fsw=1MHz.

    As a best practice, you can refer the compensation circuit in EVM schematic and just fine-tuning according to the compensation equation in tps65263x datasheet.

    3. I didn't understand why slow down the regulation response can limit the pwm jitter and avoid overcurrent thresholds tripping?

    What is the PWM jitter?  

    And don't make IC's continuous output current close to OC limit, which will cause thermal problem.  

  • Hi Zhao,

    just tried again with 261 webench.

    In pmu options i chosed PMU1_CH1

    Then clicked CHANGE DESIGN INPUTS and set

    -Vin min= 10, VinMax=14V

    -Vo1=5.0V 

    Clicked the acceptance button

    This warning showed up: "Design cannot be created with this device.  Please press OK and select a different device from the list (CR) Or click below to show why parts were not found."

    What am i missing? How can i have applied my numbers (Vo1=5V, Vo2 =1.8V, Vo3=3.3V Fsw=1Mhz) in webench? 

    ~

    For jitter i intend duty cycle variations with respect to it's average value. In constant input and output conditions there's no reason for the DC to vary, it should settle at the right duty-cycle and stay there. In real regulators noise together with non optimal loop compenstion network cause the DC to "dance" around it's optimal value. I want to avoid this "dance" to become excessive. Am not an expert in control loops, but have designed and repaired a lot and i know this is possible and preferable, and it's achieved for example by rising the one cap right from comp pin to gnd. But i guess excessive capacity will necessarily slow down the loop reaction to changes, and i don't want to afford the risk of instability. That's why i'd prefer calculated values 

    F.

  • Hi, Francesco

    1. Maybe you can try below steps:

    a. input min Vin and max Vin, then click open design.

    b. then update frequency.

    2. For reducing switching jitter, I agree with you, reducing regulation response will help.

    For TPS65263, reducing Rc or increasing Cb will help to reduce switching jitter.

    Rc will reduce bandwidth.

    Cb will make gain roll down fast beyond bandwidth, which will also help reduce jitter.   

  • Your answer tells i'm doing things right, but there must be something wrong with my PC. 

    I input the new value for Vo1, 5.0V (but i also just tried with 1.9V, same effect) and press the acceptance button: after some seconds the cited warning is shown.

    Then if i chose to see wich component(s) can not be found, an empty table is shown and i have no mean to reset the applet but shut all off and launch again.

    Anyway flash applets are being abandoned, so no interest in digging into these issues.

    What i still don't understand is why equations from datasheet lead me to ten fold higher Rc values and 5 to ten fold higher Cb values than both the ones found in the schematics on page 29 and the other ones presented as default in webench.

    There may be a typo or something missing with the datasheet, or more likely some error of mine. Did anyone else here find these formulas useful?

    F

  • Hi, Francesco

    Could you send me your calculation? you can put your calculation in a EXCEL file and attach here.

    For the Rc calculation, it is related with selection of crossover frequency fc and Vout. Usually TI set fc to 1/20 of Fsw, and your Vout is big, so you will get big Rc.   

    For Cb calculation, it is related with ESR of Cout, what is ESR you used?

  • Hi.

    Have done my calculation twice, by hand, and have no time to do everything again.

    But you can confirm them if you want, and i'd appreciate you to do so. So that you may help me understanding where i eventually fail or miss something.

    I proceeded this way:

    1) selected a reasonable unified inductor value, 4.7uH that allowed me to chose Fsw from a wide range with reasonable ripple current and to chose from quite small high current inductors: chosed SPM5030T-4R7M-HZ from Vishay

    2) chosed 10 uF MLCCs one on each branch's power supply pin. this 30uF total, even once derated by temp/voltage effects, should sustain quite well 1Mhz operation. Input voltage ripple under full load confirms this with it's reasonable amplitude

    3) selected 100 uF standard grade X7R MLCCs for output on every out, to cope with high voltage&temperature derating and support high load steps with little Output voltage effects.

    4) added a (BLM31KN471SN1L) ferrite bead isolated second  identical100uF tank MLCC on every out. Feedback was taken from first cap. Fb ESR is low so i preferred having a more reliable control loop and little drops on real outputs. I appreciate your opinion about this choice.

    5) 1Mhz fsw was chosen for various reasons (syncronization with another fixed 1Mhz switcher first)

    6) fc= 1/10 fsw (mid way in datasheet suggested valid range)

    7) Vout/Iout ratio was used for RL values, for each range. Iout was the expected maximum value.

    8) Followed design guide  at paragraph 8.2.2.4 Loop Compensation on page 31,32  and used suggested values for gains etc.

    Ended up with

    -Rc(1v8)~212kohm, Rc(3v3)~389kohm, Rc(5v0)~589kohm, Rc(0v9)~106kohm, Rc(1v8)~212kohm, Rc(3v3)~389kohm, Rc(5v0)~589kohm, Rc(0v9)~106kohm,

    -Cc~2n2 for all branches, 

    -Cb(1v8)~120pF, Cb(3v3)~64pF, Cb(5v0)~42pF, Rc(0v9)~236pF, 

    -C1(1v8)~79pF, C1(3v3)~35pF, C1(5v0)~22pF, C1(0v9)~318pF,   (I can not remember based on with ESR value i did calculations. But i gues i used a reasonable value from datasheet of used X7R MLCCs, that show a certain variability across families, in the range of few to tens of mOhm.

    Thanks & bye

    F.

  • Hi, Francesco

    Some comments:

    1) selected a reasonable unified inductor value, 4.7uH that allowed me to chose Fsw from a wide range with reasonable ripple current and to chose from quite small high current inductors: chosed SPM5030T-4R7M-HZ from Vishay

    [Zhao] I think 4.7uH is ok. But inductor selection should be follow the rule of "8.2.2.1 Output Inductor Selection of datasheet", set inductor ripple current to ~30% of max loading.  

    2) chosed 10 uF MLCCs one on each branch's power supply pin. this 30uF total, even once derated by temp/voltage effects, should sustain quite well 1Mhz operation. Input voltage ripple under full load confirms this with it's reasonable amplitude

    [Zhao] Yes, 10uF for input cap is good enough. And EVM is also using 10uF input for each channel.

    3) selected 100 uF standard grade X7R MLCCs for output on every out, to cope with high voltage&temperature derating and support high load steps with little Output voltage effects.

    [Zhao] Agree, bigger Cout can improve the load step performance.

    4) added a (BLM31KN471SN1L) ferrite bead isolated second  identical100uF tank MLCC on every out. Feedback was taken from first cap. Fb ESR is low so i preferred having a more reliable control loop and little drops on real outputs. I appreciate your opinion about this choice.

    [Zhao] For avoiding misunderstanding, I attach the below picture that shows the correct placement for bead.

    Bead should isolate tps65263 output from loading end, and we should make the tps65263's feedback trace is taken from Cout(C2&C3).

    And I think you are correct.  

    5) 1Mhz fsw was chosen for various reasons (syncronization with another fixed 1Mhz switcher first)

    [Zhao] I think it is ok, but please note the minimum on time limitation when Vout is small, we should calculate the on time (LX high level time) that should be larger than minimum on time.

    6) fc= 1/10 fsw (mid way in datasheet suggested valid range)

    [Zhao] the bandwidth and crossover frequency(fc) will be 100kHz. Actually, I think fc=100kHz is a little big for peak current control mode, then the phase margin would be affected by the high-order poles. Usually we set fc=~50kHz for peak current mode.  

    In summary,

    For Rc value you calculated, it think it is incorrect, it is too big, I think your problem is at fc selection and Cout. Rc is related with Cout, different Cout leads to different Rc, in TPS65400 EVM schematic, the Cout is only 2*22uF, so EVM's Rc value is small.    

    For Cb value you calculated, I think it is correct.

    In addition, after calculation, we should do the AC simulation by using TINA Average Model to make sure that there is enough phase margin, see below link.

    http://www.ti.com/product/TPS65263/toolssoftware

  • Thank you Zhao!!

    Your help was great! It helped me confirming my choices and gave me a mean to do things better. You helped me a lot with this!

    Will afford learning Tina in future, have not that much time now; so will go for a trial and error on existing hardware. Your hints confirm that a reasoned compromise between empirically found optimal values, datasheet guideline and knowledge of components behaviour over voltage and temperature will lead  to the best possible results.

    Think this thread may be closed.

    Bye

    Francesco

  • Hi, Sir

    If you have further questions, please post it here, then this thread will be open again, and E2E system will inform me.