TPS65911: PWRON timing after V5IN and VCC7

Hi

I got new info for this issue. Please see the following waveform.

PWRON set to high at the following timing. Is this possible timing?

Or could you give us the correct timing if this timing is not acceptable?

Best Regards,

Koji Hamamoto

Hi, Koji,

  Please check its datasheet section (copied below) for normal PWRON signal active level:

6.5.1.1 Device POWER ON Enable Conditions
The device POWER ON enable conditions are as follows:
• None of the device POWER ON disable conditions are met.
• PWRON signal low level
• Or PWRHOLD signal high level

Hi Phil,

I am sorry. My explanation was not so good.

I understand about Fig 5-2.

Our customer sequence is as I attached above.

The customer requirement is the output of PMIC should be startup with PWERON signal after V5IN and VCC7 startup.

BUT, the issue for some sample the output (SW1 and all other output ) does not startup at the above sequence.

So, my question whether there is any sequence between PWRON signal and VCC7(other power input) or V5IN .

or Which power supply must be turned on in advance to accept the PWRON signal input?

For example, do we need to make some wait time of PWRON signal after or before VCC7 and V5IN startup?

Best Regards,

Koji Hamamoto

Hi, Koji,

  The PWRON input is designed for the external button to power on/off the device; it needs >100mS low level to power on/off the device with VCC7 and V5IN normally presented; it's not a reset or enable signal to make the device in active mode. 

  It looks like the cold reset input signal HDRST should be used in customer's design; the reset release (falling edge) generates a POWER ON enable condition during a fixed delay tDOINT1. 

  Please let's know if you have further questions. 

Hi Phil,

Thank you for your reply.

Is this described at anywhere of datasheet?

Now this issue has been occurred on customer production board, it's difficult changing the sequence of HDRST.

So, I would like to know exactly how we should set(sequence) PWRON signal and VCC7 (V5IN).

As you mentioned,we need to set either of the follwoing sequence of startup. Is my understanding correct?

(Before VCC7/V5IN startup we need to set PWRON signal to high or low , then in the state of that we need to keep PWRON signal to high or low for over 100ms.)

Best Regards,

Koji Hamamoto

Hi, Koji,

  From what you told and what I see, following sequences are needed:

1.  With VCC7 (V5IN) and all other input power supplies presented.
2. PWRON signal needs to be low for at least 100mS and then rising and staying high.
3. PWRHOLD signal needs to rise high after the "Switch On sequence" as showing by pictures below: 

Hi Phil,

Thank you for your reply.

The sequence you answered is as bellow, is this correct?

If so, for example how is the following sequence?

Because on the customer board PWRON signal is normally high (pulled up) during the power supply applied.

So , PWRON signal will be the following sequence on the customer board.

Is this acceptable?

Best Regards,

Koji Hamamoto

Hi Phil,

Do you have any update? Our customer are waiting for your answer.

Best Regards,

Koji Hamamoto

Hi, Koji,

  I'm sorry for the late answer; but unfortunately, the answer is: No, PWRON must be high when PWRHOLD rsing up. 

Hi Phil,

I appreciate your answer. But it is bad news for me.

Please give us a little more detail as we need an explanation (solution) to the customer.

Is it okay if PWRON stay high when VCC7 is started up, as you said PWRON must be high when PWRHOLD rise up?

For example, are the following waveform acceptable?

Best Regards,

Koji Hamamoto

Hi Phil,

Thank you. I have another question but I will create the new post.

Best Regards,

Koji Hamamoto