LM1085: Datasheet C_out ESR recommendations conflict.

Hi Joseph, 

I would recommend having the big tantalum or AI electrolytic capacitor close to the output of the device to inject the zero needed for stability and having ceramic capacitors close to the load to minimize the ESR especially at higher than the 500KHz frequency to lower the voltage change when applying the load. 

I agree with you that the way that the datasheet explains this is a little confusing. 

Regards, 

Jason

Hi Joseph,

This is a follow-up with your response. Do you have any concern with the proposed recommendation?

Regards,

Jason

Jason,

Your recommendation is good for new designs.  I cannot use Al Electrolytic due to wide operating range. 

I am investigating an old design that uses ceramic 10uF and 0.1uF immediately at the regulator output and ceramic at the load. The design uses the adjustable version of the part and does not add a decoupling cap to the ADJ pin. The regulator and load are within 2inch of each other and make use of pwr/gnd planes.

I expect to see instability, but do not. What is needed to prompt the regulator into instability?  Are there circumstances in which the tantalum cap is not necessary?  

Hi Joseph, 

I post a new reply last week but it did not show up. I apologized for the issue. 

For stability related issues, it's usually marginal and it could be seen at some extreme conditions. For this device, it recommends using the cap that has a slightly higher ESR than the ceramic caps, but this is no data or plot to define the stability area so it's hard to say if tantalum cap is really required. 

Does the old design has a series resistor with the capacitors?  For the stability check, we would recommend having a fast load transients check. Here is an app note that explains the details. 

http://www.ti.com/lit/an/slva381b/slva381b.pdf

Regards, 
Jason Song

Jason,

The old design has no series resistor. It will be easy to replace Cout with tantalum and that rework is in progress.

Thanks for the ap note. This shows stability is related to transient current.  I have found instabilities associated with inrush currents.

I suspect stability is related to temperature as well - agree? 

Would a stability stress test be at temps higher or lower than room temp?

Do you have a suggestion for how to physically implement the transient current load pulse?  I don't see those details in the ap-note.

Many Thanks,

Joe M

Jason,

This is very helpful information.

If ESR*C = 1/(500x10^3Hz), then 22uF provides ESR = 1/(500*10^3*22*10^-6) = 10^3/(500*22) = 91mOhms, not 500mOhm. Agree?

For 10uf, I get 200mOhm, which is a typical tantalum cap ESR.

I've removed ceramics at the LDO and inserted 22uF tantalum with 200mOhm ESR, which meets the minimum 91mOhm ESR requirement.

1.8Vout is from 3.3V and 3.3V is from 5.0Vin.  These devices are co-located closely.

In this case, LM1085-ADJ(1.8) is creating 1.8V from 3.3V that is output from LM1085-ADJ(3.3).

The ceramic 10uF Cin for LM1085-ADJ(1.8) was replaced with 22uF tantalum as well to ensure Cout of LM1085-ADJ(3.3) has sufficient ESR.

Because of LMN1085 co-location, Cout of LM1085-ADJ(3.3) is 44uF, requires 45mOhm min. Two tan caps are 200mOhm each, 100mOhm combined ESR.

It seems that if each tantalum cap individually has acceptable ESR on its own, then every combination of acceptable ESR tantalum caps will be OK. Agree?

Now I need to include the ceramic caps of the Load that are fairly closely co-located.

Hi Joe, 

Sorry, it's a typo, you are right. With a 22uF capacitor, the ESR needed is around 90mOhms. 

In your application, you have two stages, one if from 5V -> 3.3 and the other is 3.3 -> 1.8. For each stage, you could have ceramic capacitors as Cin close to the input pins to lower the source impedance; you should also have the tantalum capacitors with proper ESR close to the output pin of each stage to satisfy the stability required for this device. 

Yes, the combination of the two identical tantalum cap will still meet the ESR requirement if the individual one has the acceptable ESR. 

Regards, 

Jason Song

Jason,

I believe I CANNOT have ceramic Cin when the two regulators are co-located, because the Cin of stage 2 is effectively also Cout of Stage 1, which cannot tolerate ceramic. 

I think you agree, but please confirm.

The same should be true for C_bulk capacitors placed at the load, but still located close to the LDO. 
The resistance for 1/2 oz copper, 50mm wide and 50mm long is 1.25 mOhm, which is quite small compared to 200mOhm TanCap ESR.
The sum (trace resistance and low ceramic cap ESR)  is then in parallel with tan cap ESR and
lowers the effective resistance, which then fails to create zero at 500KHz.
Agree?

What is the headroom voltage for LM1085?

Joe

Hi Joe, 

If you have two LDO really close to each other like you mentioned "co-located", we general not recommending to have ceramic capacitors in parallel as this may bring down the ESR looking from the output of the first stage LDO. But if the ceramic capacitors' value is very small and the lowest ESR from the ceramic is far away from the bandwidth of the LDO (>10MHz), it will not affect the ESR within the bandwidth of the LDO when in parallel, then you can have them. 

This may also help to answer your 2nd question, the parasitic and small resistance introduced by the trace can only create an ESR dip at very high frequency. 

Does it make sense?

Regards, 
Jason Song

You are more than welcome.