UCC28700-Q1: Wait State

Hello Shinichi-san,

Thank you for your interest in the UCC28700-Q1 PSR flyback controller.

Yes, you are correct: the "wait state" refers to a low-power stand-by condition of the controller which happens during the long dead-time periods between switching cycles at low frequency.  At high switching frequencies, the controller bias power is always on and Idd = ~2.1mA +Qg*fSW (IC bias + gate charge).  This controller operates in DCM so at light loads the switching frequency is reduced and there is a lot of dead time between pulses. 

If the controller stayed fully enabled during these dead times, the bias power would represent a significant portion of the input power and light-load efficiency would be very low.   Since the IC is not doing anything significant during the dead-times, the full bias power would be wasted. To improve light-load efficiency, the controller detects the low frequency condition and disables most of the control functions not used during the dead time and enters the "Wait" state.  This reduces the Idd current from 2.1mA down to 85uA to save considerable bias power. When it is time for the next switching cycle, the IC comes out of the Wait state back into the Run state and provides another gate-drive pulse for the next cycle.  At the end of the demagnetization interval of that cycle (the flyback time), it goes back into the Wait state for the remainder of the period.

The Wait timing is determined by the switching frequency needed to keep Vout in regulation, based on the output loading.  As load gets lighter, the control law (page 14 of datasheet) directs lower fSW, which is the same as a longer switching period.  The controller delivers the gate pulse, then goes into the Wait state for the remainder of the period.  An internal period timer is one of the few functions that is kept "alive" during the Wait state to time out the period and start an new cycle.   As load is further reduced, the Wait state gets longer.  As load is increased, the Wait-state time gets shorter.  At some period, it is not practicable to change back and forth rapidly between  Run and Wait so the controller then stays in the RUN state continuously.   I am not certain, but I believe the Vcl threshold for entering and exiting the Wait mode is 44kHz at the lower end of the Ipp curve of the Control Law (around Vcl = 2.2V).  There is some threshold hysteresis to avoid chattering between modes.

Regards,
Ulrich