1. In D/S, it specifics that the sink/source current with certain condition is +/-10A. Is this a minimum current? What's the condition of the VDD-VEE with +/-10A?
Is there diagram chart to show the gate driving capability current vs. VDD-VDD(V)?
2. If ext. Miller Clamp function is not used, how to deal with CLMPI pin for good noise immunity?
3. If both APWM and AIN are not used, how to deal with them for good noise immunity?
Regards
Brian