UCC21750-Q1: Enable time

christophe yve

Part Number: UCC21750-Q1

Hi,

What is the opening delay of the PWM outputs when Enable in is set to low?
- Immediately 
- After a delay ??µS
- Synchronized with PWM state change

Thank you for the help.

over 5 years ago

0 Audrey Dearien7 over 5 years ago

TI__Expert 4875 points

Hi Christophe,

The EN pin has the same deglitch filter as IN+ or IN-, but takes highest priority, as shown in Table 1 of the datasheet. If the EN pin is set to low, it is immediately reflected at the output (after the propagation delay).

Regards,

Audrey

0 christophe yve over 5 years ago in reply to Audrey Dearien7

Prodigy 40 points

Hi Audrey,

If the EN pin is set to high and if the PWM is not synchronised with the EN pin .

How are the outputs configured ?

Examples below :

Thank you for your help.

0 christophe yve over 5 years ago in reply to christophe yve

Prodigy 40 points

0 Audrey Dearien7 over 5 years ago in reply to christophe yve

TI__Expert 4875 points

Hi Christophe,

The first solution you show is correct. See the attached simulation with output results where IN is the input, RST_N is the nRST/EN pin voltage and VOUT is the output voltage.

Regards,

Audrey

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UCC21750-Q1: Enable time