Hello!
Will there be no issues connecting the EN to VREG? Customer is inquiring if this will be alright. His design uses a voltage divider to the EN pin from VIN to GND but wishes to remove the resistors to minimize PCB real estate.
I was thinking that (1) the power sequence may affect the "calibration" discussed in D/S 7.3.2, and (2) the internal LDO's current capability may not suffice if it will be used as a supply to the EN or affect its stability in some way. I am, however, unable to verify or analyze further.
Can you please help or advise if it's OK to connect EN to VREG?
Thanks a lot for your help.
Regards,
Elisha