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LM5069: Leakage current of internal zener diode (12V) at 75degC

Part Number: LM5069

In our design, Front end protection circuit has a mosfet which gate is controlled by LM5069. In LM5069 internal zener diode is used for VGS regulation as 12V. Shall I get the leakage current of zener diode over temperature rise since the leakage current will affect the gate of the mosfet. our ambient will be around 85degC.

  • Hi Maharasi,

    12V is the typical clamp voltage of the internal zener diode. The leakage current should be applicable before the diode starts clamping the voltage. May be, I am missing your question. What is your concern ?

    BR, Rakesh

  • Hi Rakesh,

    As you said , We need to look into the period before clamping. During normal operation with no transient applied, but at 75degC what will be the leakage current of internal diode.

    Thanks in advance,

    Maharasi Paramasivan.

  • Hi Maharasi,

    In normal operation, the diode sinks all the charge pump current i.e. 16uA (typ)

    BR, Rakesh

  • Hi Rakesh,

    The datasheet is mentioning that during normal operation to maintain the mosfet in ON condition the 16uA charge pump is biasing the gate. But you are telling that the 16uA is sinked by the zener. Pls clarify.

    Thanks in advance,

    Maharasi Paramasivan

  • Hi Maharasi,

    When the MOSFET is fully turned-ON, the GATE does not need current expect to compensate the GATE leakage. So, the charge pump current gets shunted by the zener clamp.

    BR, Rakesh

  • Thank you Rakesh for your support.

    Now it is clear that During mosfet Gate rise, the charge pump 16uA is charging the gate capacitance. after turning on the mosfet the 16uA is shunted by zener to maintain 12V.
    1. If so is there any chance or any case the internal zener may misbehave like sinking more current more than 16uA which may lead the mosfet to go into linear region..

    In our design to clamp the transient to 31V external zener was used between gate and IC gnd, whose leakage varied depend upon the temperature (it is actually seen during testing time).
    So the leakage current increased on increasing temperature which resulted in mosfet linear operation Due to that power dissipated for a long time and mosfet failed.Then we have changed the zener diode with another part and tested. That high temperature leakage issue gone.

    Once again during continuous testing we have seen a mosfet failure happened at unknown time which can not be found during testing. So we are debugging what might be the reason behind the failure.
    2. And also what are all the cases seen as faults by LM5069. Does Only current limit exceed for a particular time is considered as fault or even power limit exceeding a particular time also considered as a fault.

    Regards,
    Maharasi Paramasivan.

  • Hi Maharasi,

    We never seen such leakage issue with the internal diode. 

    1. Regarding external Zener diode.. select the part which has max. reverse current <1uA across temperature. It will be good to get the details from the Zener manufacturer.

    2. LM5069 treats both current limit and power limit as fault mode of operation

    BR, Rakesh

  • HI Rakesh,

    Zener that we have used has less then 1 uA  reverse leakage current @85degC

    May i know whether you meant reverse current or reverse leakage current?

    And Tell me whether my circuit has any problem.

    Rpwr = 18.2Kohm

    Rsns = 1mohm

    Mosfet used AUIRFS3107TRL (back to back for reverse protection)

    zener for clamping at gate MMSZ4717T1G

    Vin = 28V

    Iload = 20A

    Cload = 2mF

    Tambient = 85 degC

    Rthjc = 3.4 W/degc (includes mosfet 0.4w/degc + thermal pad 1.3w/degC + heat sink 0.75w/degC + thermal vias 0.92w/degC)

    Timer capacitor = 1.33 uF

    Gate resistance =10 ohm

    We are not able to figure out when and why the mosfet is failing. If u have an idea with these info pls share with us.

    Regards,

    Maharasi Paramasivan.

  • Hi Maharasi,

    Seems to be the problem of FET SOA and not the Zener clamp. Have you added soft-start circuit at GATE to support 2mF load. ?

    Have you verified your design using design calculator ? If not- please fill and send me for review. it is available at http://www.ti.com/product/LM5069/toolssoftware

    BR, Rakesh

  • HI Rakesh,

    Wish you a happy new year!!!!

    I have filled the Design Calculator and attached with this reply.

    Pls review and tell me if any point you notice.

    Thanks in advance,

    Maharasi P.

    LM5069_Design_Calculator_REV_C.xls

  • Hi Maharasi,

    Wish you a happy new year to you too...

    FET SOA margin is just 0.1 and it has to be >1.1 to ensure FET protection. Have you gone through the training videos while filling the design sheet ?

    You need to add dv/dt startup circuit as shown in the front page of the LM5069 datasheet.

    Can you share your schematic as well

    BR, Rakesh