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LM3409: PFET choose of LM3409

Feng bin Su
Expert 8760 points
Part Number: LM3409

Hi team,

My customer has some question about our PFET choose suggestion as below description in our datasheet.

  • What is the function of Cf capacitor which is putting between Vin pin and Vcc pin? Is it for the frequency response of LDO? Customer would like to know whether there is any side effect since removing it at PFET Qg>30nC and why it will improve the peak current detection performance since it is removed?
  • Why can it also improve the  peak current detection performance since CF be connected from the VCC pin to the CSN pin? 

Customer would like evaluate which way is more suitable for their mass-production product. Thanks.

  • 0
    TI__Mastermind 28655 points

    Hello,

    "What is the function of Cf capacitor which is putting between Vin pin and Vcc pin? Is it for the frequency response of LDO? Customer would like to know whether there is any side effect since removing it at PFET Qg>30nC and why it will improve the peak current detection performance since it is removed?"  It has nothing to do with the frequency response of the LDO.  Connecting Cf to Vin when Qgate is higher can affect the leading edge current sense.  When the MOSFET turns on the current to charge the gate will go through the CS resistor if  Cf is connected to Vin and can cause a false leading edge trip.  Connecting Cf to CSN avoids this since the current to charge the gate does not go through the CS resistor.  If connected to CSN there will be an offset in the current sense since VCC current runs through the CS resistor.

    "Why can it also improve the  peak current detection performance since CF be connected from the VCC pin to the CSN pin?" See above, it may not improve it however it will prevent false current trip due to the charging of gate during turn on.

    At low LED currents the offset will be more noticeable however a smaller PFET with lower Qgate can be used so the Cf capacitor can connect to Vin.

    Best Regards,

  • 0 in reply to Irwin Nederbragt
    TI__Expert 8760 points

    Hi Irwin,

    Thank for your information.

    At present, the following two material numbers are used for MOSFETs. Qg is between 26nC (typ) ~ 40nC (max). The error value may make Qg lower than or greater than 30nC. If CF is changed to VIN to CSN according to the specifications, is there any other risks ? Thank you.

    FDMS86163P

    SiR871DP

  • 0 in reply to Feng bin Su
    TI__Mastermind 28655 points

    Hello,

    There should be no issues besides what is mentioned above, the slight offset.

    Best Regards,

  • 0 in reply to Irwin Nederbragt
    TI__Expert 8760 points

    Hi Irwin,

    Customer has verified with higher Qg mosfet and didn't observe a abnormal behavior if they still tie the CF from Vcc to Vin.

    As talked in datasheet, it will have the possibility of false triggering of the peak detection comparator since the Qg>30nC .

    Would you still suggest them to move VCC pin to the CSN pin for preventing process variation at mass production since they have tested it for a while?

    Thank for your help.

  • 0 in reply to Feng bin Su
    TI__Mastermind 28655 points

    Hello,

    It is a recommendation if Qgate is above a certain level.  There are lot variations in both the LM3409 and the MOSFET.  Behavior also changes with operating points and temperature.  If they want to leave it I would recommend they take good oscilloscope pictures of the leading edge of the current sense and gate waveform to see how much margin there is over all their operating conditions.

    Best Regards,

  • 0 in reply to Irwin Nederbragt
    TI__Expert 8760 points

    Hi Irwin,

    There are two follow-up questions from customer.

    Could you kindly provide your suggestion about the choice of mosfet?

    1.For LM3409, the difference in MOS Qg value will affect the connection of peripheral lines, would you suggest customer to connection of circuit which should be based on the chosen of the Qg of mosfet  in typical value or max value?

    2. What will the "false trigger" mentioned in Datasheet 9.1.8 induce the system problem? Does it induce the output current unstable or any other system error?
    They would like to know more about the what will be happened after false triggering ?

    Thank for your kindly help.

  • 0 in reply to Feng bin Su
    TI__Mastermind 28655 points

    Hello,

    1)  I would use the maximum value.  With a proper oscilloscope connection the current sense leading edge can be observed to see how much margin there is.

    2)  The false trigger is the current sense tripping on the leading edge, this will cause a minimum on-time resulting in the average current dropping.  Once the current drops the next cycle may operate correct however the overall average will end up being lower due to the leading edge current trip.

    Best Regards,

  • 0 in reply to Irwin Nederbragt
    TI__Expert 8760 points

    Hi Irwin,

    Please refer the below figure for leading edge waveform with vin and csn situation.

    May I know the margin of limitation of it? Not sure whether it has shown on datasheet or not.

    If our understanding is correct, the current dropping of false trigger is dependent with the pwm cycle? Thank for your help.

  • 0 in reply to Feng bin Su
    TI__Mastermind 28655 points

    Hello,

    It appears the leading edge on these two pictures is about 60 ns.  Typical leading edge blanking is 115 ns for the LM3409.  It would also be helpful to see the actual current ramp after the MOSFET turn on to see how much ripple there is.  Is there a gate resistor used?

    It appears it will function fine either way however worst case analysis should be looked at.

    Regardless, going with the datasheet recommendations is best.

    Best Regards,

  • 0 in reply to Irwin Nederbragt
    TI__Mastermind 28655 points

    Hello,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out)

    Best Regards,