TPS40055 - What waveforms are expected at each IC pin?

Mganzetti,

I don't have a document describing the expected waveforms on each pin, but I can provide you with a list here:

Pin 1 (KFF) - This pin is a sinking input.  It should be a DC voltage at 3.48V

Pin 2 (RT) - This pin is a sourcing output.  It should be a DC voltage at 2.5V

Pin 3 (BP5) - This pin is a sourcing output.  It should be a DC voltage at 5V (4.7 - 5.5V)

Pin 4 (SYNC) - This pin is a high-impedance Input.  If used for SYNC, it should have a square wave forced on it.  If not used, it should be connected to GND and 0V.

Pin 5 (SGND) - This is the 0V (ground) reference for the IC.  It should be a DC voltage = 0V

Pin 6 (SS/SD) - This is a sourcing input.  During shutdown this pin should be 0V.  During start-up, this pin should ramp from 0V to 3.5V (3.3 - 3.7V).  During normal operation this pin should be a stead 3.3 - 3.7V.  During an Over-Current condition this pin is also used for reset timing.  In Over Current, this pin will ramp from 0V to 1V 7 times then attempt a normal start-up ramp.  If you are observing 7 similar ramps + 1 shorter or taller ramp in repetative cycles on this pin, the IC is entering OCP during start-up.

Pin 7 (VFB) - This is a high-impedance input.  It is the inverting input to an internal error amplifier with the non-inverting input connected to the internal refeence.  During steady-state operation, this pin should be 0.7V

Pin 8 (COMP) - This is a sourcing Input/output.  Is is both the output of the internal error amplifier AND the input to the PWM comparator.  During normal operation it should be a near DC voltage between 1V - 3V.  During a fault, it is forced low.  During the above described OCP fault, it should be low during the 7 similar ramps then rising rapidly when the SS/SD voltage reaches about 0.7V on the "different" ramp.

Pin 9 (PGND) - This is the high-current return for the low-side Driver.  It should be a DC voltage of 0V.

Pin 10 (LDRV) - This is a sourcing output.  During normal opeation, this pin should produce a pulse-train at the switching frequency with voltage of 0V and 9-11V.  It should be complimentary to HDRV and SW.  In the TPS40055 controller LDRV will be "HIGH" during a fault condition.

Pin 11 (BP10) - This is a sourcing output.   This pin should be a DC voltage equal to 9-11V

Pin 12 (SW) - This is a high-impedance input.  This pin follows the switching node and also serves as the high-current return for the high-side driver.  During normal operation it should be a pulse train between 0V and the Input Voltage.  It should be complimentary to LDRV

Pin 13 (HDRV) - This is a sourcing output.  This pin provides a floating drive voltage referenced to the switching node.  During normal operation, this pin should generate a pulse train between 0V and the Input Voltage + 9-11V  It should be Synchronized to SW and complimentary to LDRV

Pin 14 (BOOST) - This is a sourcing output / Sinking Input.  This pin provides power to the high-side driver AND recharges the flying "bootstrap" capacitor.  During normal opeation this pin should be a pulse train between 9-11V and the Input Voltage + 9-11V .  It should be synchronized to SW & HDRV.

Pin 15 (VIN) - This is a sinking input.  This pin provides power to the TPS40055 controller.  It should be a DC voltage equal to the input voltage.

Pin 16 (ILIM) - This pin is a sinking input. This pin provides a reference voltage to determine over-current conditions.  This voltage should be a DC voltage equal to the input voltage MINUS 10uA * the resistance between this pin and the input voltage.

The first waveform I would suggest checking is the SS/SD voltage as your description sounds like an over-current protection failure.

thanks i'll do all checks