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TPS650830: TPS650930 - Alternate configuration for VR5 controller??

Vigneshwar Raj
Prodigy 245 points
Part Number: TPS650830
Other Parts Discussed in Thread: CSD87381P, ,

Hi,

We are Using TPS650930 PMIC part for CFL H mobile platform application. We need the following details regarding VR5 voltage controller,

Query 1: As per the datasheet VR5 voltage controller is dedicated for +5V supply generation. We need 0.95V to be generated from that VR. Is there any opion available to configure VR5 controller at 0.95V? If there is a option, how to configure it?

Query 2: The exact output voltage for High drive pin (DRVH1, DRVH3, DRVH4 & DRVH5) and Low drive pin (DRVL1, DRVL3, DRVL4 & DRVL5) of respective VR controller is not available in data sheet. In the datasheet, the recommended voltage range is specified as 26V for DRVH and 5V for DRVL. Our application Vin (Pin N6) voltage is +12V. Kindly share the exact DRVH & DRVL output voltage.

Query 3: Is there any calculation sheet available for TPS650930ZAJT VR controller?

Note: We have already signed NDA for PMIC's with TI.

 

Regards,

Vigneshwar Raj

  • 0
    TI__Guru 64821 points

    Hello,

    Answer 1:  In order to change the voltage a custom part would need to be ordered.  Please see datasheet section 6.3.13.6 Output Voltage Control: "If you need a different output voltage configuration from the specified default, please contact TI to generate you a custom part."

    Answer 2:  I do not have this information.  Intel provides a reference design and recommendation for which FET switches to use.  Also, TI recommends the CSD87381P, see section 7.2.2.1.3 in the datasheet).

    Answer 3:  In the application section of the datasheet, section 7, there are equations for calculating recommended inductance and current limit resistance. 

    Regards,

    Chris

  • 0 in reply to Chris Sterzik
    Prodigy 245 points

    Hi Chris,

    Reply for answer-2: Since we are new to this Intel architecture design we need the evaluation module for this particular IC. Is this possible to test with evaluation module of TPS650930?

    Regards,

    Vigneshwar Raj

  • 0 in reply to Vigneshwar Raj
    TI__Guru 64821 points

    I will need to verify what is currently available.  I will provide an answer by close of business tomorrow, 1/29.

    Regards,

    Chris

  • 0 in reply to Chris Sterzik
    TI__Guru 64821 points

    I was not able to find an evaluation module of the TPS650930.  Will the TPS650830 be an adequate substitute (http://www.ti.com/tool/TPS650830EVM-095)?

    Regards,

    Chris

  • 0 in reply to Chris Sterzik
    Prodigy 245 points

    Hi chris,

    If the only major difference between TPS650930 and TPS650830 is VR1 rail voltage level and switching frequency, then it could be better if checked with TPS650830EVM-095. Please verify.

    Answer 1: Reply:- In my case VR5 is not used for generating V5ADS3 (Used external +5V source), then how to terminate/handle VR5 Bank without affecting the PWROK & PWRGD signals (Since it is internally mapped as per Figure 5-5. Power-Good Tree Logic)

    Pin No. Pin Description Connection
    K8 VSC Feedback from External 5V source
    C12 ENC Un-affected (SLP_S3#)
    N5 VIN5VSW Connected to external 5V source
    M5 EN5VSW Power Good from External 5V source
    L7 VINVR5 How to terminate these lines in TPS650930 VR5 Bank?
    M2 ENVR5
    K5 ILIMVR5HS
    L5 ILIMVR5LS
    N3 PGNDVR5
    M1 DRVHVR5
    N4 DRVLVR5
    L4 FBVR5N
    G4 FBVR5P
    M4 PGVR5
    N2 SWVR5
    M3 VBSTVR5

    Regards,

    vigneshwar

    Figure 5-5. Power-Good Tree Logic

  • 0 in reply to Vigneshwar Raj
    TI__Guru 64821 points

    I am still investigating this issue.  My initial thinking was to simply disable the VR5 regulator and mask the power good signal before enabling the regulator.  Unfortunately, in my investigation I found some differences in the description around VR5 between the TPS650830 and TPS650930 that I need to reconcile.  I will provide an update next Monday.


    Regards,
    Chris

  • 0 in reply to Chris Sterzik
    TI__Guru 64821 points

    Hello,

        If you are replacing VR5, then the external 5V supply must provide a power good signal (V5ADS3_PG) and this is connected to ENA.  None of the Power Good signals (except for DPWROK) will go high until VR5 Pgood is masked. You will need to write to this register via I2C.  I will get some clarification about VR5 connections in the next couple of days.  I will provide an update on Wednesday.

    Pin

    Description

    Comments

     

    VINVR5

     GROUND

     

    PGNDVR5

    GROUND

     

    ENVR5

    GROUND

     

    ILIMVR5HS

     FLOAT

     

    ILIMVR5LS

     FLOAT

     

    DRVHVR5

     FLOAT

     

    SWVR5

     FLOAT

     

    DRVLVR5

     FLOAT

     

    VBSTVR5

     FLOAT

     

    FBVR5P

     FLOAT

     

    FBVR5N

     FLOAT

     

    VIN5VSW

    Connected to external 5V

     

    EN5VSW

    Connected to PGOOD from external 5V

     

    PGVR5

     PGVR5 is disconnected (floating).  PGOOD from external 5V is connected to V5ADS3_PG

     

    ENA

    V5ADS3_PG.  Connected to PGOOD from external 5V

     

    VSC

    Datasheet error.  In Figure 5-5, comparator C:  V5A should be input for external PRIMCORE_VR .  V5A_DS3_PG-> PRIMCORE_PG, MV5AD3PG -> MVPRIMCOREPG

     

    ENC

    V3.3A_PCH_PG (unchanged)

    Regards,
    Chris

  • 0 in reply to Chris Sterzik
    TI__Guru 64821 points

    I have updated the fields.  Effectively, the input is grounded and the outputs and feedback can be left floating.

    Regards,

    Chris