TPS546D24A: phase shift between three independent TPS546D24A

Jerry,

The TPS546D24A does not include a "reset to default" function, but you can use TI FUSIONS's import a project feature to overwrite any changes that you made.  The project file should include resetting the PIN_DETECT_OVERRIDE function back to it's default of F2F1 to ensure that pin-detection is enabled and any resistors on the board will update their respective PMBus values on the next power cycle.

After importing the project, store the project values to NVM, wait at least 100ms for the NVM write to complete, and then cycle AVIN power on the TPS546D24A.

When synchronizing multiple single-phase designs to a common clock:

1) Decide if one of the TPS546D24A devices will be used to generate that clock, or if the common clock will be provided externally.

If one of the TPS546D24A devices will generate the clock, it should be Pin Programmed, or PMBus programmed to set SYNC_CONFIG to SYNC_OUT.  This is done either with PMBus programming, or by the resistors selected on the ADRSEL pin.  If PMBus programmed, make sure the SYNC_CONFIG bit in PIN_DETECT_OVERRIDE is set to "0" to disable pin-detection of SYNC_CONFIG.

2) Set the other TPS546D24A devices (or all of them if an external CLOCK will be used) to SYNC_IN through Pin Strapping or PMBus programming.

3) Make sure all TPS546D24A devices are programmed to the same switching frequency by PMBus programming or Pin Strapping.  If setting the switching frequency via PMBus programming, make sure the FREQUENCY_SWITCH bit in PIN_DETECT_OVERRIDE is set to 0.  If using an external SYNC signal, the external SYNC frequency must be within +/- 20% of the programmed switching frequency.

4) For Single Phase devices, the INTERLEAVE PMBus function is uses to select the Phase shift between the SYNC signal and the internal oscillator that controls the timing of the SW node. 

The high-byte of INTERLEAVE command identifies the "Group" for digital discovery purposes but has no functional impact, it can be set to any value desired from 00 to FF.  It is intended to allow the user to identify which clock a group of devices is using.

The low-byte of INTERLEAVE command defines the phase position using 2 nibbles.  The lower nibble (bits 3:0) define the Position within the Group and the upper nibble (bits 7:4) define the Number in group, or the size of each position.  The TPS546D24 recognizes:

Number in Group of 2, 3 and 4, which represents phase shifts of 180 degrees, 120 degrees and 90 degrees per position

Position in group of 0 to Number in Group - 1.

This allows the selection of phase positions of 0, 90, 120, 180, 240, and 270 while the SYNC_EDGE bit in SYNC_CONFIG allows a device to be synchronized to the rising or falling edge of SYNC.

For equal spacing of 3 devices to a common clock, you can set INTERLEAVE values of 00x0, 0031, and 0032 to set phase positions of 0, 120, and 240, which is effective when all of the output voltages are close in value.  If the duty cycles or loading currents are significantly different, non-equal spacing may provide a better solution.