TPS65400: TPS65400 Status Byte Register: Bit 0

hi Keith,

Application engineer, Lishuang Zhao, will check it and give feedback on Monday.

Hi Keith,

1. For this byte, bit 0, we don't have any more detail about the fault or warning.Please capture and upload some waveform of Switcher 1 and Switcher 2, including Vin, Vout, SW, BST and PG.

2. Do you use Switcher 3 and 4? Are they okay?

3. Have you restarted to check the status? Because any bits set in the status register remain set even if the fault condition is removed or corrected. The fault bits in the status register remain set until one of the following occur: (Details can be checked in section 8.5.2.4 Fault Monitoring page 38 on datasheet.)

• The device receives a CLEAR_FAULTS command.

• A RESET signal is asserted by either issuing a SOFT_RESET or by asserting/deasserting the CE terminal.

• Bias power is removed from the PMBus device.

Thanks,

Lishuang

Hello,
Thank you for your help.  Here are answers to your questions:

1. For this byte, bit 0, we don't have any more detail about the fault or warning. Please capture waveform of Switcher 1 and Switcher 2, including Vin, Vout, SW, BST and PG.
[KK] I thought these were all in the document except the BST signal. PG was deasserted as the status was not good.

2. Do you use Switcher 3 and 4? Are they okay?   
[KK] These are not used

3. Have you restarted to check the status? Because any bits set in the status register remain set even if the fault condition is removed or corrected. The fault bits in the status register remain set until one of the following occur: (Details can be checked in section 8.5.2.4 Fault Monitoring page 38 on datasheet.)
[KK] Status is reset using CLEAR_FAULTS command. When the fault is only during start-up for a limited number of cycles the current overflow bit disappears. Otherwise it stays set.

Thank you, Keith

We found that these actions fixed the problem:

1. lowering the switching frequency
2. increasing input voltage
3. delay in turning on the 2^nd switcher