TPS40055 losing regulation under load

Massimo,

Without looking at what the converter is doing, it's hard to say for certain why this would be occuring, but I can propose a hypothisis that you can verify if you have an oscilloscope:

The TPS4005x family of controllers uses a pulse - pulse current limit scheme that both detects the precense of a over-current condition and terminates the current switching pulse to prevent power stage damage.  The scheme includes a 7-cycle "deglitch" counter before the controller shuts-down, times out and then attempts a restart.  This "deglitch" counter increments when the TPS4005x's PWM pulse is terminated by Over Current detection and decrements when the PWM pulse is terminated by normal operation.

This scheme is designed to limit the peak power stage current to an acceptable level, avoid "nuicense" tripping of OCP and limit power dissipation when the ouptut is shorted.  However the scheme does have a limitation.  When very near the OCP trip point, the scheme can enter into a state where the PWM pulse alternates between tripping on an OCP pulse and then tripping on a maximum duty cycle pulse. 

When the part has entered into this state, the PWM pulse is alternately defined by peak current limit and maximum duty cycle.  The fault "deglitch" counter alternates back and forth between 2 values.  In this state:

FB is less than 0.7V

COMP is more than 3.0V

Switch Node (SW and HDRV) alternate between a LONG (Max duty cycle) and Short (OCP trigger) pulse widths.

WHen the load is removed, the duty cycle returns to is prior value.

Since the TPS40055 and TPS40057 controllers maximum duty cycle is dependant on the UVLO programming and current input voltage, it might be possible to alleaviate this issue by:

1) Incerasing the UVLO voltage (Vin(min) from Rkff calculation)

2) Increasing current limit set point (Increase Rilim)

Massimo,

Have a wonderful weekend.

If you're seeing alternating LONG - SHORT pulses on the ouptut of a Voltage Mode Control PWM converter under normal operation, you likely have a small problem in your control loop called bi-stable operation (or bi-modal operation).  This occurs when the combination of the gain and phase shift from the PWM switch (Switching Node) to the PWM comparator (COMP on the TPS4005x family) can produce stable, alternating duty cycles.

The L-C filter and error amplifier compensation loop are intended to attenuate the switching waveform from the switch node back to the PWM comparator (Error amplifier output) however, then can't entirely attenuate this switching waveform, producing some ripple on the PWM comparator's input at the switching frequency.  When this ripple is in-phase with the switching action, it is not an issue and typically increases the effective ramp slope, improving stability.

When this ripple is heavily phase shifted from the switching action due to ultra-low ESR output capacitors and high gain in the error amplifier needed to achieve fast transient response, the phase shift can reduce the effcetive ramp slope and even create 2 stable operating points (or modes) that the PWM alternates between to maintain regulation.

If you are observing these alternating Long-Short pulses, I would recommend modifying your error amplifier compensation network to reduce the Output to Control (Error Amplifier) gain at the switching frequency.