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Original question:

TPS7B68-Q1: Input capacitor range

TPS7B68-Q1: Using electrode cap as Input capacitor

NOBUO FUJIHARA
Genius 9355 points
Part Number: TPS7B68-Q1

Hi Jason,

My customer asked additional question regarding to input capacitor for TPS7B68-Q1.

They want to use electrode cap with below spec.

- 100uF

- ESR=0.9ohm(100kHz@25degC), 14ohm(100kHz@-40degC)

Is there any concern in terms of stability, load transient, drop-out voltage or other performance?

Best regards,

  • 0
    TI__Mastermind 23361 points

    Hi Fujihara-san,

    I am looking into this question and I will get back to you by Friday.

    Regards,

    Jason Song

  • 0 in reply to Jason Song
    TI__Genius 9355 points

    Hi Jason-san,

    Thanks for the reply.

    May I ask additional question regarding to Cdelay range?

    From system requirement, customer need to increase Cdelay to 0.22uF.

    Though no spec for Cdelay max value, in 8.2.2.4 it describes typical value as from 100pF to 100nF.

    8.2.2.4 Power-Good Delay Period
    The power-good delay period is set by an external capacitor (CDELAY) to ground, with a typical capacitor value
    from 100 pF to 100 nF. Calculate the correct capacitance for the application using Equation 2.

    Could you check if 0.22uF for Cdelay is OK?

    Best regards,

  • 0 in reply to NOBUO FUJIHARA
    TI__Mastermind 23361 points

    Hi Fujihara-san,

    What's the reason that you would like to have the electrode capacitor at the input of the LDO? The datasheet recommends the input capacitor to be in the range of 10-μF to 22-μF and a 0.1-uF bypass. I would strongly suggest you follow the recommendation in the datasheet. 

    Having an electrode capacitor with high ESR (14Ohms at 100KHz) could increase the source impedance and this will result in a smaller headroom from Vin to Vout comparing to the low ESR input capacitor. Lower Vin and Vout headroom generally reduce the AC performance of the device including load transient and PSRR. The dropout of the LDO is a DC specification and it will not be affected by the input capacitor. Normally the stability is primarily related to the output capacitor. 

    For the Cdelay, the delay is set by charging the Cdelay capacitor to a target voltage. Having a bigger than recommended capacitor should be okay but it may result a bigger error when calculating the delay with equation 2 provided in the datasheet. 

    Regards, 
    Jason Song

     

  • 0 in reply to Jason Song
    TI__Genius 9355 points

    Hi Jason-san,

    Thanks a lot for your support.

    I would like move to off line discussion over e-mail.

    Best regards,