TPS3703-Q1: Time delay 150us

Hi Hayashi-San, 

i will be glad to help you with your inquiry 

but first could you share a timing diagram of the implementation? I am trying to understand if the 150us delay correspond to the sense detection time or release time. 

The 150us refers to an absolute value or a target limit, target limit means that the signal can be either faster or slower than the given value. 

Thanks 

Antony Carvajales

Hi Antony-san

Thank you for responose.

Hi Hayashi-San, 

Thanks for providing the time range for the timing requirement 

Using the attached figure as reference, please confirm that by delay time you are referring to tPD (delay time to assert a reset ) and latch is required for the tD (Reset release time) 

Figure is an screenshot from TPS3703-Q1 datasheet page 8

http://www.ti.com/lit/ds/symlink/tps3703-q1.pdf

Hi Antony-san

Thank you for response.

My customer wants to release output by himself.

I attached timing chart and block diagram

I think this is possible with the connection "Figure 35. Window Voltage Monitoring with RESET Latch".

(Excluding delay time and logic inversion)

Best Regards,

Koji Hayashi

Hayashi-San, 

Thank you for sharing the detail timing diagram. 

TPS3703 can meet the latching requirement with the integrated feature, but the sense timing is fixed to 30us max; for the 100us sense delay an RC will be required. is RC delay acceptable or high accuracy for sense delay is needed?

please let me know what is driving the need for 100us sense delay? also let me know the 5V rail under voltage threshold. 

Thanks 

Antony 

Hi Antony-san

Thank you for response.

RC delay is acceptable.

There is no problem if the total variation is 100μs to 200μs.

Previous variation was 100μs to 400μs.

100μs ~ 200μs is OEM requirement.

What do you mean that  "5V rail under voltage threshold".

Best Regards,

Koji Hayashi

Hayashi-San, 

It is great that RC is acceptable for sense delay. 

for the voltage option we have two options 

• TPS3703C7500DSERQ1: this variant has an undervoltage trigger point of 4.65V and overvoltage of 5.35V
• TPS3703E4080DSERQ1: this variant has only undervotlage with reference of 0.768V, meaning that the 5V UV need to be adjusted using external resistor divider from 5V.

Thanks, 

Antony 

Hi Antony-san

Thank you for response.

My customer only want UV.

So,I recomend them TPS3703E4080DSERQ1.

Hayashi-San, 

The cap will need to be connected across the low side resistor to increase the glitch immunity. the cap size will depend on the resistor value (R2) and the voltage across R2. 

R2 and R1 value depends on the required trigger point, guidelines to select/calculate the resistors can be found in section 9.1.4 (Adjustable Voltage Thresholds) in the datasheet http://www.ti.com/lit/ds/symlink/tps3703-q1.pdf

Hi Antony-san.

Sorry, I had a misunderstanding.

Delay in SENSE is unacceptable.

Is it difficult to respond to the following customer requirements with this IC alone ?

>Customer request delay: 100μs～200μs, monitoring 5V, LATCH.

Best Regards,

Koji Hayashi

Hi Antony-san

Thank you for quick response.

I understand that using 0.2nF for the CT pin would take about 150μs.

I also understand that a separate IC is required to LATCH.

I will think about it.

Best Regards,

Koji Hayashi