TPS3828-Q1: /RESET cannot be released if WDI is toggled during /RESET active.

John11513

Part Number: TPS3828-Q1
Other Parts Discussed in Thread: TPS3828

Hi experts,

My customer reports a problem with TPS3828's watchdog function. Unlike typical application, customer use this device in a special way: the WDI input is driven by a specific circuit during some specific time to disable the watchdog timer in some condition. So WDI input can be toggled even during /RESET active. The issue is they found the /RESET signal cannot be released if WDI input is pulsed with period of 50ms (50% duty cycle). Below is the screen shot of test waveform. I am wondered if the duration of the WDI transition MUST longer than delay time?

Thank you

John

over 5 years ago

0 Abhinav.Sharma over 5 years ago

TI__Genius 9375 points

John,

I believe you need to allow enough time for the WDO transition to take effect which is the delay time. This is as you expected.

Thanks,
Abhinav.

0 John11513 over 5 years ago in reply to Abhinav.Sharma

TI__Expert 5720 points

Hi Abhinav,

Thank you for reply. But I don’t think so. As my understanding/RESET signal should be released as soon as WDI transition is detected. Why the device kept /RESET in low state because of WDI transition?

Thank you!

John

0 Abhinav.Sharma over 5 years ago in reply to John11513

TI__Genius 9375 points

Hi John,

As related to this paragraph in the datasheet:

I believe this is the behavior you are referencing. The RESET will be stuck logic low in this case, and if you need a workaround, you can use an external FET. Let me know if this is not what you meant.

Thanks,
Abhinav.

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TPS3828-Q1: /RESET cannot be released if WDI is toggled during /RESET active.