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TPS54160: RT/CLK input: Is there a dutycycle spec?

Fernando Fonseca1
Prodigy 40 points
Part Number: TPS54160

Hi,

Is there a dutycycle range for the RT/CLK input I should adhere to? I don't seem to find one in the datasheet.

Thanks in advance for your support.

Fernando Fonseca

Electronics Eng.

  • 0
    TI__Expert 4555 points

    Hello Fernando,

    The external clock square wave amplitude must transition lower than 0.5V and higher than 2.2V on the RT/CLK pin and have an on-time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. I would highly recommend reading 8.3.16 section of the datasheet to implement the external clock circuit. 

    Please close this thread if you think my response answered your question.

    Best Regards,

    Ankit Gupta

  • 0 in reply to Ankit Gupta95
    Prodigy 40 points

    Still none the wiser. I'll rephrase the question.What is the duty cycle range specified for the ext clk input? Surely someone must have validated this and therefore someone must know? Thank you

  • 0 in reply to Fernando Fonseca1
    TI__Expert 4555 points

    Hello Fernando,

    As I have mentioned in my last post, there is only min-on time and min-off time spec has to adhere for valid external clock signal. There is no duty cycle spec as it is not needed actually in this case. The duty cycle will vary with the chosen frequency, and the user has to make sure of having enough duty cycle to meet min-on and min-off time spec. I hope this will help!

    Please close this thread if you think my response answered your question. Thanks!

    Best Regards,

    Ankit Gupta

    Application Engineer