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TPS53513: SW node jitter over expected

Penn Zhang
Intellectual 1180 points
Part Number: TPS53513

Hi Sir,

TPS53513 in the design as below:

Vin=12V Vout=0.95V Fsw=500KHz L=1uH Iload=6.4A

Jitter is 28%, over 20%, could you give some suggestions on this?

Thank you.

  • 0
    TI__Mastermind 18510 points

    Hi, Check the layout first. How about the FB line? is it far away switching node/Bst node and refer to Ground plane? and what's the output caps used?

    Also you can check transient and ripple performance, generally if both are well, a little big jitter is no problem. of course you also can try to improve the Fsw and add more output caps to try..

    Yuchang

  • 0 in reply to Yuchang Zhang
    TI__Guru**** 191445 points

    Penn,

    Normally jitter is defined as variation of the on time from cycle to cycle when the input and load conditions are fixed.  This is shown as varian of the falling edge of the switch node waveform.  TPS53513 uses DCAP3 control.  For DCAP3, there is no internal oscillator, so there may be variations in both on time and off time shown as variation of both rising and falling edge of the SW node waveform.  So DCAP3 will inherently have more perceived jitter than fixed frequency converters.  In your case, there may be some issue also with your remote sense and layout.  For best results, the FB return should be terminated close to the IC AGND, not remotely at the load.  You can try to modify a board to see if it improves.