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UCC28251: Low duty cycle operation

Martin Haberzettl1
Prodigy 60 points
Part Number: UCC28251

Hello everyone,

i am currently testing the UCC28251 for a Full bridge converter with synchronous rectification.
It has to work steadily from almost 0% to around 90% dutycycle as the output has to be regulated over the full voltage range with very low ripple
Ideally, the device should always regulate continuously and not in bursts of pulses for as low voltages as possible.
The Oscillator Frequency is currently fixed at 200 kHz

I have noticed that at very low duty cycles the UCC28251 shows some non-ideal behaviour:

  • The pulse width can not be smaller than 62ns, which translates to 1,2% duty cycle.
    When trying to get lower, the OutA and OutB Pulses simply stop
    I cannot find any information in the Datasheet regarding minimum pulse width. Is this intentional behaviour?

  • Between a pulse width of 62ns and 100 ns, there seems to be a discontinuity.
    At this point, small noise translates to a great jump in pulse width of 30 to 40 ns between pulses, which is a huge relative change.

An alternative possible way for low-duty-cycle operation would be to reduce the switching frequency when low duty cycle is needed.
The problem is, that from the datasheet i don't see a way to continuously/linearly reduce the switching frequency depending on an external signal.
Also, when the frequency is changed, the Ramp amplitude changes accordingly which would also influence the loop gain.

My Questions now are:

  • Is the UCC28251 suitable for low duty-cycle operation below 1% or should I take a look at other Parts?
  • Do you have any tips to improve it's behaviour?
  • Is there a way to continuously reduce the switching frequency and at the same time keep the ramp amplitude constant?


Thank you very much in advance.

Kind Regards
Martin Haberzettl

  • 0
    TI__Mastermind 31580 points

    Hi Martin,

    The UCC28251 has leading edge blanking feature which is typically 60ns. This means that the minimum pulse width will close to this value allowing for propagation delays.

    Most power supply applications are a fixed output voltage and the controller only has to go to very low duty cycles at light load where is can enter into the mode you describe with no adverse effects to the output voltage.

    Many analogue controllers will struggle to give consistent performance at dusty cycles in the 1 to 3% range. The control signal range is close to the minimum value and will become more sensitive to noise.

    To modify the frequency you could try splitting the RT resistor into two and placing a signal level mosfet in parallel with the lower resistor to switch between two settings. Alternatively you could try placing an adjustable current sink on the RT pin which will program the switching frequency.

    To achieve more precise control at narrow duty cycles I suggest you consider a digital controller like the C2000 where you can have more precise quantised steps.

    Regards

    Peter

  • 0 in reply to Peter Meaney
    Prodigy 60 points

    Hi Peter,

    thank you for your fast Reply.

    Sadly, using digital regulation is not an option for the current project.

    It is good to know that the frequency can be reliably changed by a current-sink and not only by a resistor. I have not found this in the datasheet.
    Using a signal level mosfet would only allow an instantanious change of frequency, not a gradual one.

    This would also theoretically allow to use two equally controlled current sources: one for the switching freqency and one for the ramp, so the PWM gain does not change.


    Also, for your Information:
    I am currently trying out a way to resolve the issue by modifying the output waveforms.
    By delaying the rising edge by 100 ns while keeping the falling edge, I should theoretically be able to overcome the unwanted behaviour near zero pulse width.
    Let's see if this brings any reasonable improvement.

    Regards

    Martin