CCS/UCD3138: Ramp complete status

RAMP_COMP_STATUS is a raw status, rather than a latched one. On the UCD there are a few of these bits, and they are generally so transient as to be useless.  I suspect this is one of those.  Since your solution seems reasonable and works, I'd continue to use it. If you want to look for more adventure, you can try the RAMP_COMP_INT_STATUS register.  It says it is latched, but it is most likely clear on read.  Some of the clear on read ones have clear prioritized over read.  With those, we recommend using the interrupt bit in the central interrupt module for polling.  I'm not sure whether this is one of those.  If it is, and you use it directly, you will get rare intermittent failures when you read at exactly the wrong clock cycle when the ramp has just finished.  So again, just stick with what you've got.