TPS40055 switching waveforms

Massimo,

The waveforms you describe are consistant with the pulse-by-pulse current limit issue I described before.  400ns is the minimum pulse width tha an over-current condition can detect while 2.24us is likely the maximum duty cycle at 24V input given the UVLO programming.

While I appreciate the schematic and layout to help solve your issue, I would caution you in the future - the TI forum is a public access forum and anyone reviewing the forum will be able to view your schematic and PCB.

That said, I believe I know the source of your issue.  The TPS40055 controller uses a comparator between the SW Pin (Pin 13) and the ILIM pin (Pin 16) to detect over-current.  In your layout R8 and R7 appear to connect to the input voltage traces fairly far from the drain voltage of the high-side FET (Q1).  Any voltage differences between the drain voltage of the high-side FET and the VIN voltage sensed by ILIM appears to the IC as voltage drop across the high-side FET.  Under load, the seperation between the Q1 drain and the VIN connection point for R7 is effectively increasing the current limit.

A couple of things you can do:

1) Improve layout to provide R7 with a kelvin connection to the drain of Q1

2) Increase R7 + R8 to increase allowable voltage drop before current limit

3) Increase UVLO by increasing R23, R27 and R28.  This will increase maximum duty cycle

You may also want to review the 15nF snubber capacitor.  This capacitor is charging and discharging from 0V to 24V and back to 0V each switching cycle.  This dissipates 2x 1/2 CV^2 * Fsw = 15nF * 24V^2 * 300kHz = 2.6W  typically snubber capacitors in the 500 - 2000pF are most effective, depending on the parasitics around the switching node.  The target is for the capacitance to be no more than 3x the parasitic capacitance at the switching node.