Other Parts Discussed in Thread: TPS24751
Hi,
On the datasheet it is said that:
- GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, that is, the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the internal FET remains off.
Also this is written:
- The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the internal FET gate to ground with approximately 1 A of current. The fast-trip circuit holds the internal FET off for only a few microseconds, after which the TPS2475x turns back on slowly, allowing the current-limit feedback loop to take over the gate control of the internal FET. Then the hot-swap circuit goes into latch mode (TPS24750) or auto-retry mode (TPS24751). Figure 35 and Figure 36 illustrate the behavior of the system when the current exceeds the fast-trip threshold.
Could you clarify the following?:
- After a fast trip threshold event occurs, does the TPS24750 latches OFF; or does it first quickly disables the internal FET, then enables it at the current limit threshold until Ctimer reaches 1.35V? From the datasheet, first sentence makes me think that the internal FET is disabled quickly and not enabled again. However the second sentence mentions that the E-Fuse starts turning ON slowly after a fast trip threshold.
- It is my understanding that fast trip threshold is first sensed from PG pin because the FLT pin is controlled by Ctimer voltage which is not charged when a fast trip occurs. Is this correct?
Regards,
Zeki
