Hello,
I'm currently evaluating the performance of a prototype design, originally made by someone else (and no longer contactable), using the TPS16630 (QFN package). This is primarily used in a 24V industrial device, to enforce a current limit of approx 5.5A to downstream circuits (externally connected circuits).
We've experienced some issues with startup, under full-load - that have been identified as relating to the device's thermal regulation during startup, effectively due to the inrush current and short-term power-dissipation across the device. We have plans to vastly improve the power handling, through better PCB layout (heatsinking of the device) and switching to the TSSOP version. I am aware also of the design calculator tool for this device, to help estimate whether a given design *should* be able to start-up or not.
However, my question specifically relates to the dVdT capacitor. I understand the the function of this component, but it has been noted that the datasheet:
- mentions that "The fastest output slew rate of 24V/500 μs can be achieved by leaving dVdT pin floating." (section 9.3.1); but
- also lists 10nF as the recommended minimum value, according section 7.3
Is there a reason for this recommended minimum value?
Other than increasing the output slew-rate, is there any other known side-effect, or behavior that I should be aware of, by having a dVdT capacitor less than 10nF (or open/floating)?
Thank you kindly in advance.
Dave