Hello, We'd like to use TPS3430 in a latching application as per TI's published document SNVA837. In summary, We're looking for WDO to stay asserted LOW upon the failure of DWI to reset the watchdog timer.
In addition we'd like to be able to reset the latched WDO output, restoring it to it's normal (disabled or active watchdog) operating conditions. To accomplish this, we are thinking to connect the TPS3430 as follows:
VDD1/2 - 3.3V
WDI - GPIO input from NXP microprocessor
WDO - output with 10k pullup resistor
CWD - N/C
CRST - 5 nF capacitor to ground and open drain buffer from WDO
SET 0 - GPIO input from NXP microprocessor
SET 1 - 3.3V (HIGH)
The intended schematic is identical to what's provided in SNVA837 and also on p. 24 of the spec sheet for TPS3430 except for SET 0, which we're routing to a GPIO pin on an NXP micro.
Our understanding of this is as follows:
The TPS3430 can be powered up with SET 0 in either a high or low state successfully. If SET 0 is HIGH upon power up, the device will remain disabled and WDO will remain HIGH until SET 0 is set LOW, at which point the watchdog timer will begin with tWDL ~ 22.5 ms and tWDU ~ 55 ms (with tolerance bands on these nominal values.) If SET 0 is LOW upon power up, the watchdog timer will begin after a brief initialization.
If the window is ever missed, WDO will be asserted LOW (open drain), and remain latched LOW as long as the other pin states do not change.
If, from this WDO-asserted LOW (open drain) state, SET 0 is ever set HIGH, the device will be disabled entirely and WDO will be set back to HIGH.
If, from the device's disabled state, SET 0 is set back to LOW, the watchdog timer will once again initialize with a 22.5 ms / 55 ms valid window.
Is this understanding correct?
Thanks!
Blake
