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UCD90320: UCD90320 configure as Fault Pin GPI functionality and behaviour

Sai Loo
Expert 5110 points
Part Number: UCD90320

Hi team,

My customer is evaluating UCD90320 and has the following enquiries:

In datasheet, page 19:

• Configured as Fault Pin GPI fault enable functionality must be set to enable this feature. When set, if there is no fault on a fault bus. The FAULT pin is digital input pin and it monitors the fault bus. When one or more UCD90329 devices detect a rail fault, the corresponding FAULT pin is turned into active driven low state, pulling down the fault bus voltage and informing all other UCD90320 devices of the corresponding fault. This behavior allows a coordinated action to be taken across multiple devices. After the fault is cleared, the state of the FAULT pin reverts to that of an input pin.

Customer would like to know regarding the last sentence " After the fault is cleared, the state of the FAULT pin reverts to that of an input pin.”

what actions need to be taken for the fault to be considered “cleared”; specifically does a GPI configured as a “Latched Statuses Clear Source” clear the fault? If not, can you please explain to me what needs to occur before the UCD90320 device considers the fault to be “cleared”?

Would also like to know what happens after a full power cycle, if a fault drive a system power cycle.  Does this get logged in NV memory?

Regards

SK Loo

  • 0
    TI__Guru 66120 points

    HI

    Fault pin is to cascading among multiple device. if you system does not have more than one device, you do not need fault pin.

    Please read section 3 of http://www.ti.com/lit/an/slva908/slva908.pdf

    The fault to be cleared is mean: the rail has no UNDER_VOLTGAE or OVER_VOLTAGE fault.

    For example: if at any given time, a given rail's voltage is below UNDER_VOLTAGE threshold, this rail is reported as UV_FAULT. this fault is clear if the rail is recovered which can be achieved by shutdown the rail and turn the rail back on.

    The GPI as" Latched Statuses Clear Source" is to clear the status but it does not clear the fault.

    Yes, if a fault was present during the operation, this fault would be logged into NV if it is enabled. By default, all faults are logged.

    Regards

    Yihe

  • 0 in reply to yihe
    TI__Expert 5110 points

    Thanks Yihe,

    In customer application, they have an external FPGA that we interface to the IO’s of the UCD90320. They would like to implement a way for the UCD90320 to report back to the FPGA if a fault on any rail occurs so it can take appropriate actions if needed. It looks like using the Fault pin functionality would best fit this purpose since they could simply wire it to an IO pin on our FPGA. However, is there a better way to implement this? They tried using an LGPO, but it didn’t seem to be possible to tie every possible latched fault state to a single LGPO.

    regards,

    SK Loo

  • 0 in reply to Sai Loo
    TI__Guru 66120 points

    Hi

    They can do this via single LGPO as well. They can use different LGPO to handle each fault separately. Then use all these LGPO as input for the final LGPO which is connected to FPGA.  Basically, they have to define multiple LGPO, but only one LGPO need have a physical pin.

    Hope this helps.

    Regards

    Yihe

  • 0 in reply to yihe
    TI__Guru 66120 points

    Hello

    We haven't heard from you for a while and assumed that the issue has been solved. please reply here if further help is needed.

    Regards

    Yihe