Hi
I have a design based on LM27403 to convert 9-16V in to 3V3 out. It was designed using Webench, and I have lately confirmed the design values using the design spreadsheet.
My problem is that the circuit starts either very slowly or not at all, depending on the applied load. It looks as if the initial current inrush into the output capacitor trips the current limit feature, causing hiccup mode to occur. This results in only a few switching cycles occurring every 7ms or so (the hiccup hold-off period). If the applied load is very low (a few 10s of mA) the circuit eventually starts: each hiccup cycle slightly raises the output voltage a little until it becomes high enough for the inrush current to eventually be low enough that the circuit starts properly from there. If the applied load is greater (but still low compared to the design current) the circuit doesn't start at all, because the load bleeds the output capacitor during the hiccup hold-off period, enough to stop the few switching cycles per period raising the net output voltage at all.
The current limit was initially set for 14A (which is where I'd like it to operate, since this is a little above the system maximum). If the current limit is raised to, say 40A (by increasing the resistors into CS+, CS-), the circuit starts correctly. So I guess my fallback position is just to disable current limiting, but this is not ideal in this application. I'd ideally expect the current-limit/hiccup feature to be prevented whilst the circuit is starting up, but this seems not to be the case.
The output capacitor is a 1000uF electrolytic in parallel with a 47uF multi layer ceramic. The ceramic is intended to lower switching ripple by shunting the ESR of the electrolytic (which is 90mR). 1000uF is much larger than the minimum suggested by the design tool, however the system is modular and (owing to capacitors on each module) may have a large and indeterminate load capacitance, which I hadn't expected to be an issue. In any case, removing the electrolytic doesn't fix the problem, presumably because the inrush current is determined by the MLC ESR and not by the output capacitance per se.
The circuit forms part of a multi-rail supply, and it is important that the rails come up in sequence. To this end, I have a soft-start of 4ms programmed using an SS capacitor.
I am not using resistors on the UVLO/EN pin to determine the starting input voltage. Rather I am driving that pin from a 3V3 logic circuit (seperately powered) to turn on the supply via a microcontroller, which also monitors the input voltage.
Is there a way of using the current limit feature at a useful level without compromising or preventing startup?
Thanks
Ian
